plat/arm: Introduce TC0 platform
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
This commit is contained in:
Usama Arif
parent
69be9154ed
commit
f5c58af653
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@ -8,6 +8,7 @@ Arm Development Platforms
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juno/index
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fvp/index
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fvp-ve/index
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tc0/index
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arm-build-options
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This chapter holds documentation related to Arm's development platforms,
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@ -0,0 +1,50 @@
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TC0 Total Compute Platform
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==========================
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Some of the features of TC0 platform referenced in TF-A include:
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- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
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to abstract power and system management tasks away from application
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processors. The RAM firmware for SCP is included in the TF-A FIP and is
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loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
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to AP SRAM).
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- GICv4
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- Trusted Board Boot
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- SCMI
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- MHUv2
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Boot Sequence
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-------------
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The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts
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executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from
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FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
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is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own
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RAM and starts executing it. The AP then continues executing the rest of TF-A
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stages including BL31 runtime stage and hands off executing to
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Non-secure world (u-boot).
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Build Procedure (TF-A only)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
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Set the CROSS_COMPILE environment variable to point to the toolchain folder.
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- Build TF-A:
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.. code:: shell
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make PLAT=tc0 BL33=<path_to_uboot.bin> \
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SCP_BL2=<path_to_scp_ramfw.bin> all fip
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Enable TBBR by adding the following options to the make command:
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.. code:: shell
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MBEDTLS_DIR=<path_to_mbedtls_directory> \
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TRUSTED_BOARD_BOOT=1 \
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GENERATE_COT=1 \
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ARM_ROTPK_LOCATION=devel_rsa \
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ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
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*Copyright (c) 2020, Arm Limited. All rights reserved.*
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@ -0,0 +1,316 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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compatible = "arm,tc0";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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stdout-path = "soc_uart0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x200>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x300>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x06000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_scmi_mem: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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};
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mbox_db_rx: mhu@45010000 {
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compatible = "arm,mhuv2","arm,primecell";
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reg = <0x0 0x45010000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <1>;
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interrupts = <0 316 4>;
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interrupt-names = "mhu_rx";
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mhu-protocol = "doorbell";
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};
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mbox_db_tx: mhu@45000000 {
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compatible = "arm,mhuv2","arm,primecell";
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reg = <0x0 0x45000000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <1>;
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interrupt-names = "mhu_tx";
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mhu-protocol = "doorbell";
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};
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scmi {
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compatible = "arm,scmi";
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method = "mailbox-doorbell";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
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shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-600", "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30140000 0 0x200000>; /* GICR */
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interrupts = <0x1 0x9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x1 13 0x8>,
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<0x1 14 0x8>,
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<0x1 11 0x8>,
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<0x1 10 0x8>;
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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soc_uart0: uart@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x1000>;
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interrupts = <0x0 116 0x4>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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vencoder {
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compatible = "drm,virtual-encoder";
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port {
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vencoder_in: endpoint {
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remote-endpoint = <&hdlcd_out>;
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};
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};
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display-timings {
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panel-timing {
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clock-frequency = <25175000>;
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hactive = <640>;
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vactive = <480>;
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hfront-porch = <16>;
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hback-porch = <48>;
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hsync-len = <96>;
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vfront-porch = <10>;
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vback-porch = <33>;
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vsync-len = <2>;
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};
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};
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};
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hdlcd: hdlcd@7ff60000 {
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compatible = "arm,hdlcd";
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reg = <0x0 0x7ff60000 0x0 0x1000>;
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interrupts = <0x0 117 0x4>;
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clocks = <&fake_hdlcd_clk>;
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clock-names = "pxlclk";
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status = "ok";
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port {
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hdlcd_out: endpoint {
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remote-endpoint = <&vencoder_in>;
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};
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};
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};
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fake_hdlcd_clk: fake-hdlcd-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25175000>;
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clock-output-names = "pxlclk";
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};
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ethernet@18000000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x18000000 0x0 0x10000>;
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interrupts = <0 109 4>;
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c060000 0x0 0x1000>;
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interrupts = <0 197 4>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <0 103 4>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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virtio_block@1c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c130000 0x0 0x200>;
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interrupts = <0 204 4>;
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};
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dp0: display@2cc00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,mali-d71";
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reg = <0 0x2cc00000 0 0x20000>;
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interrupts = <0 69 4>;
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interrupt-names = "DPU";
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clocks = <&scmi_clk 0>;
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clock-names = "aclk";
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status = "disabled";
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pl0: pipeline@0 {
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reg = <0>;
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clocks = <&scmi_clk 1>;
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clock-names = "pxclk";
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pl_id = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dp_pl0_out0: endpoint {
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remote-endpoint = <&vencoder_in>;
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};
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};
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};
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};
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pl1: pipeline@1 {
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reg = <1>;
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clocks = <&scmi_clk 2>;
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clock-names = "pxclk";
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pl_id = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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};
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};
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};
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};
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@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <export/common/tbbr/tbbr_img_def_exp.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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/* tb_fw_config is temporarily contained in this dtb */
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tb_fw-config {
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load-address = <0x0 0x2001010>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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hw-config {
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load-address = <0x0 0x83000000>;
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max-size = <0x01000000>;
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id = <HW_CONFIG_ID>;
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};
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};
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
|
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
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* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <arm_macros.S>
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/* ---------------------------------------------
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||||
* The below required platform porting macro
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* prints out relevant platform registers
|
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* whenever an unhandled exception is taken in
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* BL31.
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*
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* There are currently no platform specific regs
|
||||
* to print.
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||||
* ---------------------------------------------
|
||||
*/
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||||
.macro plat_crash_print_regs
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.endm
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||||
#endif /* PLAT_MACROS_S */
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|
|
@ -0,0 +1,194 @@
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/*
|
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
#include <plat/arm/board/common/board_css_def.h>
|
||||
#include <plat/arm/board/common/v2m_def.h>
|
||||
#include <plat/arm/common/arm_def.h>
|
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#include <plat/arm/common/arm_spm_def.h>
|
||||
#include <plat/arm/css/common/css_def.h>
|
||||
#include <plat/arm/soc/common/soc_css_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
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||||
#define PLATFORM_CORE_COUNT 4
|
||||
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||||
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
|
||||
* plat_arm_mmap array defined for each BL stage.
|
||||
*/
|
||||
#if defined(IMAGE_BL31)
|
||||
# if SPM_MM
|
||||
# define PLAT_ARM_MMAP_ENTRIES 9
|
||||
# define MAX_XLAT_TABLES 7
|
||||
# define PLAT_SP_IMAGE_MMAP_REGIONS 7
|
||||
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
|
||||
# else
|
||||
# define PLAT_ARM_MMAP_ENTRIES 8
|
||||
# define MAX_XLAT_TABLES 8
|
||||
# endif
|
||||
#elif defined(IMAGE_BL32)
|
||||
# define PLAT_ARM_MMAP_ENTRIES 8
|
||||
# define MAX_XLAT_TABLES 5
|
||||
#elif !USE_ROMLIB
|
||||
# define PLAT_ARM_MMAP_ENTRIES 11
|
||||
# define MAX_XLAT_TABLES 7
|
||||
#else
|
||||
# define PLAT_ARM_MMAP_ENTRIES 12
|
||||
# define MAX_XLAT_TABLES 6
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
|
||||
* plus a little space for growth.
|
||||
*/
|
||||
#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
|
||||
*/
|
||||
|
||||
#if USE_ROMLIB
|
||||
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
|
||||
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
|
||||
#else
|
||||
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
|
||||
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
|
||||
#else
|
||||
# define PLAT_ARM_MAX_BL2_SIZE 0x11000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
|
||||
* calculated using the current BL31 PROGBITS debug size plus the sizes of
|
||||
* BL2 and BL1-RW
|
||||
*/
|
||||
#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
|
||||
|
||||
/*
|
||||
* Size of cacheable stacks
|
||||
*/
|
||||
#if defined(IMAGE_BL1)
|
||||
# if TRUSTED_BOARD_BOOT
|
||||
# define PLATFORM_STACK_SIZE 0x1000
|
||||
# else
|
||||
# define PLATFORM_STACK_SIZE 0x440
|
||||
# endif
|
||||
#elif defined(IMAGE_BL2)
|
||||
# if TRUSTED_BOARD_BOOT
|
||||
# define PLATFORM_STACK_SIZE 0x1000
|
||||
# else
|
||||
# define PLATFORM_STACK_SIZE 0x400
|
||||
# endif
|
||||
#elif defined(IMAGE_BL2U)
|
||||
# define PLATFORM_STACK_SIZE 0x400
|
||||
#elif defined(IMAGE_BL31)
|
||||
# if SPM_MM
|
||||
# define PLATFORM_STACK_SIZE 0x500
|
||||
# else
|
||||
# define PLATFORM_STACK_SIZE 0x400
|
||||
# endif
|
||||
#elif defined(IMAGE_BL32)
|
||||
# define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
|
||||
|
||||
#define TC0_DEVICE_BASE 0x21000000
|
||||
#define TC0_DEVICE_SIZE 0x5f000000
|
||||
|
||||
// TC0_MAP_DEVICE covers different peripherals
|
||||
// available to the platform
|
||||
#define TC0_MAP_DEVICE MAP_REGION_FLAT( \
|
||||
TC0_DEVICE_BASE, \
|
||||
TC0_DEVICE_SIZE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
|
||||
|
||||
#define TC0_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
|
||||
V2M_FLASH0_SIZE, \
|
||||
MT_DEVICE | MT_RO | MT_SECURE)
|
||||
|
||||
#define PLAT_ARM_NSTIMER_FRAME_ID 0
|
||||
|
||||
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
|
||||
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
|
||||
|
||||
#define PLAT_ARM_NSRAM_BASE 0x06000000
|
||||
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
|
||||
|
||||
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
|
||||
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
|
||||
|
||||
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
|
||||
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
|
||||
|
||||
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
|
||||
PLAT_SP_IMAGE_NS_BUF_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memprotect definitions
|
||||
******************************************************************************/
|
||||
/* PSCI memory protect definitions:
|
||||
* This variable is stored in a non-secure flash because some ARM reference
|
||||
* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
|
||||
* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
|
||||
*/
|
||||
#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
|
||||
V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
|
||||
|
||||
/*Secure Watchdog Constants */
|
||||
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
|
||||
#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
|
||||
|
||||
#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
|
||||
|
||||
#define PLAT_ARM_CLUSTER_COUNT U(1)
|
||||
#define PLAT_MAX_CPUS_PER_CLUSTER U(4)
|
||||
#define PLAT_MAX_PE_PER_CPU U(1)
|
||||
|
||||
#define PLAT_CSS_MHU_BASE UL(0x45400000)
|
||||
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
|
||||
|
||||
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
|
||||
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
|
||||
|
||||
/*
|
||||
* Physical and virtual address space limits for MMU in AARCH64
|
||||
*/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
|
||||
/* GIC related constants */
|
||||
#define PLAT_ARM_GICD_BASE UL(0x30000000)
|
||||
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
|
||||
#define PLAT_ARM_GICR_BASE UL(0x30140000)
|
||||
|
||||
/*
|
||||
* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
|
||||
* SCP_BL2 size plus a little space for growth.
|
||||
*/
|
||||
#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000
|
||||
|
||||
/*
|
||||
* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
|
||||
* SCP_BL2U size plus a little space for growth.
|
||||
*/
|
||||
#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <platform_def.h>
|
||||
#include <cpu_macros.S>
|
||||
|
||||
.globl plat_arm_calc_core_pos
|
||||
.globl plat_reset_handler
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
||||
*
|
||||
* Function to calculate the core position on TC0.
|
||||
*
|
||||
* (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
|
||||
* (CPUId * PLAT_MAX_PE_PER_CPU) +
|
||||
* ThreadId
|
||||
*
|
||||
* which can be simplified as:
|
||||
*
|
||||
* ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
|
||||
* + ThreadId
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_arm_calc_core_pos
|
||||
/*
|
||||
* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
|
||||
* look as if in a multi-threaded implementation.
|
||||
*/
|
||||
tst x0, #MPIDR_MT_MASK
|
||||
lsl x3, x0, #MPIDR_AFFINITY_BITS
|
||||
csel x3, x3, x0, eq
|
||||
|
||||
/* Extract individual affinity fields from MPIDR */
|
||||
ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
|
||||
/* Compute linear position */
|
||||
mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
|
||||
madd x1, x2, x4, x1
|
||||
mov x5, #PLAT_MAX_PE_PER_CPU
|
||||
madd x0, x1, x5, x0
|
||||
ret
|
||||
endfunc plat_arm_calc_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_reset_handler(void);
|
||||
*
|
||||
* Determine the CPU MIDR and disable power down bit for
|
||||
* that CPU.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_reset_handler
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef tc0_bl31_common_platform_setup_PLAT_H
|
||||
#define tc0_bl31_common_platform_setup_PLAT_H
|
||||
|
||||
void tc0_bl31_common_platform_setup(void);
|
||||
|
||||
#endif /* tc0_bl31_common_platform_setup_PLAT_H */
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
CSS_LOAD_SCP_IMAGES := 1
|
||||
|
||||
CSS_USE_SCMI_SDS_DRIVER := 1
|
||||
|
||||
RAS_EXTENSION := 0
|
||||
|
||||
SDEI_SUPPORT := 0
|
||||
|
||||
EL3_EXCEPTION_HANDLING := 0
|
||||
|
||||
HANDLE_EA_EL3_FIRST := 0
|
||||
|
||||
# System coherency is managed in hardware
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
|
||||
# When building for systems with hardware-assisted coherency, there's no need to
|
||||
# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
|
||||
USE_COHERENT_MEM := 0
|
||||
|
||||
GIC_ENABLE_V4_EXTN := 1
|
||||
|
||||
# GIC-600 configuration
|
||||
GICV3_IMPL := GIC600
|
||||
|
||||
# Include GICv3 driver files
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
|
||||
ENT_GIC_SOURCES := ${GICV3_SOURCES} \
|
||||
plat/common/plat_gicv3.c \
|
||||
plat/arm/common/arm_gicv3.c
|
||||
|
||||
override NEED_BL2U := no
|
||||
|
||||
override ARM_PLAT_MT := 1
|
||||
|
||||
TC0_BASE = plat/arm/board/tc0
|
||||
|
||||
PLAT_INCLUDES += -I${TC0_BASE}/include/
|
||||
|
||||
TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_matterhorn.S
|
||||
|
||||
INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \
|
||||
${TC0_BASE}/include/tc0_helpers.S
|
||||
|
||||
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
|
||||
${TC0_CPU_SOURCES} \
|
||||
${TC0_BASE}/tc0_trusted_boot.c \
|
||||
${TC0_BASE}/tc0_err.c \
|
||||
drivers/arm/sbsa/sbsa.c
|
||||
|
||||
|
||||
BL2_SOURCES += ${TC0_BASE}/tc0_security.c \
|
||||
${TC0_BASE}/tc0_err.c \
|
||||
${TC0_BASE}/tc0_trusted_boot.c \
|
||||
lib/utils/mem_region.c \
|
||||
plat/arm/common/arm_nor_psci_mem_protect.c
|
||||
|
||||
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
|
||||
${TC0_CPU_SOURCES} \
|
||||
${ENT_GIC_SOURCES} \
|
||||
${TC0_BASE}/tc0_bl31_setup.c \
|
||||
${TC0_BASE}/tc0_topology.c \
|
||||
drivers/cfi/v2m/v2m_flash.c \
|
||||
lib/utils/mem_region.c \
|
||||
plat/arm/common/arm_nor_psci_mem_protect.c
|
||||
|
||||
# Add the FDT_SOURCES and options for Dynamic Config
|
||||
FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts
|
||||
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
|
||||
|
||||
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
|
||||
|
||||
#Device tree
|
||||
TC0_HW_CONFIG_DTS := fdts/tc0.dts
|
||||
TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
|
||||
FDT_SOURCES += ${TC0_HW_CONFIG_DTS}
|
||||
$(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS)))
|
||||
|
||||
# Add the HW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config))
|
||||
|
||||
override CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
override CTX_INCLUDE_PAUTH_REGS := 1
|
||||
|
||||
include plat/arm/common/arm_common.mk
|
||||
include plat/arm/css/common/css_common.mk
|
||||
include plat/arm/soc/common/soc_css.mk
|
||||
include plat/arm/board/common/board_common.mk
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <libfdt.h>
|
||||
#include <tc0_plat.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/css/css_mhu_doorbell.h>
|
||||
#include <drivers/arm/css/scmi.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
static scmi_channel_plat_info_t tc0_scmi_plat_info[] = {
|
||||
{
|
||||
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
|
||||
.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
|
||||
.db_preserve_mask = 0xfffffffe,
|
||||
.db_modify_mask = 0x1,
|
||||
.ring_doorbell = &mhuv2_ring_doorbell,
|
||||
}
|
||||
};
|
||||
|
||||
void bl31_platform_setup(void)
|
||||
{
|
||||
tc0_bl31_common_platform_setup();
|
||||
}
|
||||
|
||||
scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
|
||||
{
|
||||
|
||||
return &tc0_scmi_plat_info[channel_id];
|
||||
|
||||
}
|
||||
|
||||
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
|
||||
}
|
||||
|
||||
void tc0_bl31_common_platform_setup(void)
|
||||
{
|
||||
arm_bl31_platform_setup();
|
||||
}
|
||||
|
||||
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
|
||||
{
|
||||
return css_scmi_override_pm_ops(ops);
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* tc0 error handler
|
||||
*/
|
||||
void __dead2 plat_arm_error_handler(int err)
|
||||
{
|
||||
while (1) {
|
||||
wfi();
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* For Total Compute we should not do anything in these interface functions.
|
||||
* They are used to override the weak functions in cci drivers.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* Helper function to initialize ARM interconnect driver.
|
||||
*****************************************************************************/
|
||||
void __init plat_arm_interconnect_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Helper function to place current master into coherency
|
||||
*****************************************************************************/
|
||||
void plat_arm_interconnect_enter_coherency(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Helper function to remove current master from coherency
|
||||
*****************************************************************************/
|
||||
void plat_arm_interconnect_exit_coherency(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/ccn.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <drivers/arm/sbsa.h>
|
||||
#include <services/spm_mm_partition.h>
|
||||
|
||||
/*
|
||||
* Table of regions for different BL stages to map using the MMU.
|
||||
* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
|
||||
* arm_configure_mmu_elx() will give the available subset of that.
|
||||
*/
|
||||
#if IMAGE_BL1
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
TC0_FLASH0_RO,
|
||||
TC0_MAP_DEVICE,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
#if IMAGE_BL2
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
TC0_FLASH0_RO,
|
||||
TC0_MAP_DEVICE,
|
||||
ARM_MAP_NS_DRAM1,
|
||||
#if ARM_BL31_IN_DRAM
|
||||
ARM_MAP_BL31_SEC_DRAM,
|
||||
#endif
|
||||
#if SPM_MM
|
||||
ARM_SP_IMAGE_MMAP,
|
||||
#endif
|
||||
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
|
||||
ARM_MAP_BL1_RW,
|
||||
#endif
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
#if IMAGE_BL31
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
V2M_MAP_IOFPGA,
|
||||
TC0_MAP_DEVICE,
|
||||
#if SPM_MM
|
||||
ARM_SPM_BUF_EL3_MMAP,
|
||||
#endif
|
||||
{0}
|
||||
};
|
||||
|
||||
#if SPM_MM && defined(IMAGE_BL31)
|
||||
const mmap_region_t plat_arm_secure_partition_mmap[] = {
|
||||
PLAT_ARM_SECURE_MAP_DEVICE,
|
||||
ARM_SP_IMAGE_MMAP,
|
||||
ARM_SP_IMAGE_NS_BUF_MMAP,
|
||||
ARM_SP_CPER_BUF_MMAP,
|
||||
ARM_SP_IMAGE_RW_MMAP,
|
||||
ARM_SPM_BUF_EL0_MMAP,
|
||||
{0}
|
||||
};
|
||||
#endif /* SPM_MM && defined(IMAGE_BL31) */
|
||||
#endif
|
||||
|
||||
ARM_CASSERT_MMAP
|
||||
|
||||
#if SPM_MM && defined(IMAGE_BL31)
|
||||
/*
|
||||
* Boot information passed to a secure partition during initialisation. Linear
|
||||
* indices in MP information will be filled at runtime.
|
||||
*/
|
||||
static spm_mm_mp_info_t sp_mp_info[] = {
|
||||
[0] = {0x81000000, 0},
|
||||
[1] = {0x81000100, 0},
|
||||
[2] = {0x81000200, 0},
|
||||
[3] = {0x81000300, 0},
|
||||
[4] = {0x81010000, 0},
|
||||
[5] = {0x81010100, 0},
|
||||
[6] = {0x81010200, 0},
|
||||
[7] = {0x81010300, 0},
|
||||
};
|
||||
|
||||
const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
|
||||
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
|
||||
.h.version = VERSION_1,
|
||||
.h.size = sizeof(spm_mm_boot_info_t),
|
||||
.h.attr = 0,
|
||||
.sp_mem_base = ARM_SP_IMAGE_BASE,
|
||||
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
|
||||
.sp_image_base = ARM_SP_IMAGE_BASE,
|
||||
.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
|
||||
.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
|
||||
.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
|
||||
.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
|
||||
.sp_image_size = ARM_SP_IMAGE_SIZE,
|
||||
.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
|
||||
.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
|
||||
.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
|
||||
.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
|
||||
.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
|
||||
.num_cpus = PLATFORM_CORE_COUNT,
|
||||
.mp_info = &sp_mp_info[0],
|
||||
};
|
||||
|
||||
const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
|
||||
{
|
||||
return plat_arm_secure_partition_mmap;
|
||||
}
|
||||
|
||||
const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
|
||||
void *cookie)
|
||||
{
|
||||
return &plat_arm_secure_partition_boot_info;
|
||||
}
|
||||
#endif /* SPM_MM && defined(IMAGE_BL31) */
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
|
||||
{
|
||||
assert(heap_addr != NULL);
|
||||
assert(heap_size != NULL);
|
||||
|
||||
return arm_get_mbedtls_heap(heap_addr, heap_size);
|
||||
}
|
||||
#endif
|
||||
|
||||
void plat_arm_secure_wdt_start(void)
|
||||
{
|
||||
sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
|
||||
}
|
||||
|
||||
void plat_arm_secure_wdt_stop(void)
|
||||
{
|
||||
sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/* Initialize the secure environment */
|
||||
void plat_arm_security_setup(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/arm/css/common/css_pm.h>
|
||||
|
||||
/******************************************************************************
|
||||
* The power domain tree descriptor.
|
||||
******************************************************************************/
|
||||
const unsigned char tc0_pd_tree_desc[] = {
|
||||
PLAT_ARM_CLUSTER_COUNT,
|
||||
PLAT_MAX_CPUS_PER_CLUSTER,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return tc0_pd_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* The array mapping platform core position (implemented by plat_my_core_pos())
|
||||
* to the SCMI power domain ID implemented by SCP.
|
||||
******************************************************************************/
|
||||
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the core count within the cluster corresponding to
|
||||
* `mpidr`.
|
||||
******************************************************************************/
|
||||
unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
|
||||
{
|
||||
return PLAT_MAX_CPUS_PER_CLUSTER;
|
||||
}
|
||||
|
||||
#if ARM_PLAT_MT
|
||||
/******************************************************************************
|
||||
* Return the number of PE's supported by the CPU.
|
||||
*****************************************************************************/
|
||||
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
|
||||
{
|
||||
return PLAT_MAX_PE_PER_CPU;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
Loading…
Reference in New Issue