Merge changes I4451ca03,I29be60ec,Ia30bd332,I72fe2275,I37bd65b0 into integration
* changes: feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition feat(plat/nxp/common): add build macro for BOOT_MODE validation checking refactor(plat/nxp/common): moved soc make-variables to new soc_common_def.mk refactor(plat/nxp/lx216x): clean up platform configure file refactor(plat/nxp/common): moved plat make-variables to new plat_common_def.mk
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
f85ab34120
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@ -0,0 +1,103 @@
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# Copyright 2020-2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Include build macros, for example: SET_NXP_MAKE_FLAG
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include plat/nxp/common/plat_make_helper/plat_build_macros.mk
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# Adding platform specific defines
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$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
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ifeq (${POVDD_ENABLE},yes)
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$(eval $(call add_define,CONFIG_POVDD_ENABLE))
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endif
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ifneq (${FLASH_TYPE},)
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$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
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endif
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ifneq (${XSPI_FLASH_SZ},)
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$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
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endif
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ifneq (${QSPI_FLASH_SZ},)
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$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ}))
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endif
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ifneq (${NOR_FLASH_SZ},)
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$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ}))
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endif
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ifneq (${FSPI_ERASE_4K},)
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$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
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endif
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ifneq (${NUM_OF_DDRC},)
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$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
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endif
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ifeq (${CONFIG_DDR_NODIMM},1)
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$(eval $(call add_define,CONFIG_DDR_NODIMM))
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DDRC_NUM_DIMM := 1
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endif
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ifneq (${DDRC_NUM_DIMM},)
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$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
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endif
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ifneq (${DDRC_NUM_CS},)
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$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
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endif
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ifeq (${DDR_ADDR_DEC},yes)
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$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
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endif
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ifeq (${DDR_ECC_EN},yes)
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$(eval $(call add_define,CONFIG_DDR_ECC_EN))
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endif
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ifeq (${CONFIG_STATIC_DDR},1)
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$(eval $(call add_define,CONFIG_STATIC_DDR))
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endif
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# Platform can control the base address for non-volatile storage.
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#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
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ifeq (${WARM_BOOT},yes)
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$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
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endif
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# Selecting Boot Source for the TFA images.
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define add_boot_mode_define
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ifeq ($(1),qspi)
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$$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2))
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$$(eval $$(call add_define,QSPI_BOOT))
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else ifeq ($(1),sd)
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$$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
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$$(eval $$(call add_define,SD_BOOT))
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else ifeq ($(1),emmc)
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$$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
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$$(eval $$(call add_define,EMMC_BOOT))
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else ifeq ($(1),nor)
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$$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2))
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$$(eval $$(call add_define,NOR_BOOT))
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else ifeq ($(1),nand)
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$$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2))
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$$(eval $$(call add_define,NAND_BOOT))
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else ifeq ($(1),flexspi_nor)
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$$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
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$$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
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else
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$$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
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endif
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endef
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ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE)))
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$(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE))))
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else
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$(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE))
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endif
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@ -0,0 +1,114 @@
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# Copyright 2020-2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Adding SoC specific defines
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ifneq (${CACHE_LINE},)
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$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
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$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
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$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
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endif
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ifeq (${INTERCONNECT}, "CCI400")
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$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
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ICNNCT_ID := 0x420
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$(eval $(call add_define,ICNNCT_ID))
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endif
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ifeq (${INTERCONNECT}, "CCN508")
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$(eval $(call add_define,NXP_HAS_CCN508))
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endif
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ifneq (${CHASSIS},)
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$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
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endif
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ifneq (${PLAT_DDR_PHY},)
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$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
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endif
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ifneq (${PHYS_SYS},)
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$(eval $(call add_define,CONFIG_PHYS_64BIT))
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endif
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ifneq (${CSF_HDR_SZ},)
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$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
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endif
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ifneq (${OCRAM_START_ADDR},)
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$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
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endif
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ifneq (${OCRAM_SIZE},)
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$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
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endif
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ifneq (${NXP_ROM_RSVD},)
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$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
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endif
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ifneq (${BL2_BASE},)
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$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
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endif
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ifeq (${SEC_MEM_NON_COHERENT},yes)
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$(eval $(call add_define,SEC_MEM_NON_COHERENT))
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endif
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ifneq (${NXP_ESDHC_ENDIANNESS},)
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$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
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endif
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ifneq (${NXP_SFP_VER},)
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$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
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endif
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ifneq (${NXP_SFP_ENDIANNESS},)
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$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
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endif
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ifneq (${NXP_GPIO_ENDIANNESS},)
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$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
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endif
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ifneq (${NXP_SNVS_ENDIANNESS},)
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$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
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endif
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ifneq (${NXP_GUR_ENDIANNESS},)
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$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
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endif
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ifneq (${NXP_FSPI_ENDIANNESS},)
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$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
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endif
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ifneq (${NXP_SEC_ENDIANNESS},)
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$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
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endif
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ifneq (${NXP_DDR_ENDIANNESS},)
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$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
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endif
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ifneq (${NXP_QSPI_ENDIANNESS},)
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$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
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endif
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ifneq (${NXP_SCFG_ENDIANNESS},)
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$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
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endif
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ifneq (${NXP_IFC_ENDIANNESS},)
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$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
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endif
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ifneq (${NXP_DDR_INTLV_256B},)
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$(eval $(call add_define,NXP_DDR_INTLV_256B))
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endif
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ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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endif
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@ -33,59 +33,19 @@ BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
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# config is enabled for future use cases.
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FSPI_ERASE_4K := 0
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# Platform specific features.
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# Platform specific features.
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WARM_BOOT := yes
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# Adding platform specific defines
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$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
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ifeq (${POVDD_ENABLE},yes)
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$(eval $(call add_define,CONFIG_POVDD_ENABLE))
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endif
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ifneq (${FLASH_TYPE},)
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$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
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endif
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ifneq (${XSPI_FLASH_SZ},)
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$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
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endif
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ifneq (${FSPI_ERASE_4K},)
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$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
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endif
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ifneq (${NUM_OF_DDRC},)
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$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
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endif
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ifneq (${DDRC_NUM_DIMM},)
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$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
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endif
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ifneq (${DDRC_NUM_CS},)
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$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
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endif
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ifeq (${DDR_ADDR_DEC},yes)
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$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
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endif
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ifeq (${DDR_ECC_EN},yes)
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$(eval $(call add_define,CONFIG_DDR_ECC_EN))
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endif
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# Platform can control the base address for non-volatile storage.
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#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
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ifeq (${WARM_BOOT},yes)
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$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
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endif
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# Adding Platform files build files
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# Adding Platform files build files
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BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
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${BOARD_PATH}/platform.c
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# Adding SoC build info
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SUPPORTED_BOOT_MODE := flexspi_nor \
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sd \
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emmc
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# Adding platform board build info
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include plat/nxp/common/plat_make_helper/plat_common_def.mk
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# Adding SoC build info
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include plat/nxp/soc-lx2160a/soc.mk
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@ -36,56 +36,16 @@ FSPI_ERASE_4K := 0
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# Platform specific features.
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WARM_BOOT := no
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# Adding platform specific defines
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$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
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ifeq (${POVDD_ENABLE},yes)
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$(eval $(call add_define,CONFIG_POVDD_ENABLE))
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endif
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ifneq (${FLASH_TYPE},)
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$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
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endif
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ifneq (${XSPI_FLASH_SZ},)
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$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
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endif
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ifneq (${FSPI_ERASE_4K},)
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$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
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endif
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ifneq (${NUM_OF_DDRC},)
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$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
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endif
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ifneq (${DDRC_NUM_DIMM},)
|
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$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
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endif
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|
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ifneq (${DDRC_NUM_CS},)
|
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$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
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endif
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ifeq (${DDR_ADDR_DEC},yes)
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$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
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endif
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ifeq (${DDR_ECC_EN},yes)
|
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$(eval $(call add_define,CONFIG_DDR_ECC_EN))
|
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endif
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# Platform can control the base address for non-volatile storage.
|
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#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
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|
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ifeq (${WARM_BOOT},yes)
|
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$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
|
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endif
|
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|
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# Adding Platform files build files
|
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BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
|
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${BOARD_PATH}/platform.c
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|
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SUPPORTED_BOOT_MODE := flexspi_nor \
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sd \
|
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emmc
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|
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# Adding platform board build info
|
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include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
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|
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# Adding SoC build info
|
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include plat/nxp/soc-lx2160a/soc.mk
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ ERRATA_DDR_A011396 := 1
|
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ERRATA_DDR_A050450 := 1
|
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|
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|
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# On-Board Flash Details
|
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# On-Board Flash Details
|
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FLASH_TYPE := MT35XU512A
|
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XSPI_FLASH_SZ := 0x10000000
|
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NXP_XSPI_NOR_UNIT_SIZE := 0x20000
|
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|
|
@ -34,59 +34,19 @@ BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
|
|||
# config is enabled for future use cases.
|
||||
FSPI_ERASE_4K := 0
|
||||
|
||||
# Platform specific features.
|
||||
# Platform specific features.
|
||||
WARM_BOOT := yes
|
||||
|
||||
# Adding platform specific defines
|
||||
|
||||
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
|
||||
|
||||
ifeq (${POVDD_ENABLE},yes)
|
||||
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
|
||||
endif
|
||||
|
||||
ifneq (${FLASH_TYPE},)
|
||||
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
|
||||
endif
|
||||
|
||||
ifneq (${XSPI_FLASH_SZ},)
|
||||
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
|
||||
endif
|
||||
|
||||
ifneq (${FSPI_ERASE_4K},)
|
||||
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
|
||||
endif
|
||||
|
||||
ifneq (${NUM_OF_DDRC},)
|
||||
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
|
||||
endif
|
||||
|
||||
ifneq (${DDRC_NUM_DIMM},)
|
||||
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
|
||||
endif
|
||||
|
||||
ifneq (${DDRC_NUM_CS},)
|
||||
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
|
||||
endif
|
||||
|
||||
ifeq (${DDR_ADDR_DEC},yes)
|
||||
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
|
||||
endif
|
||||
|
||||
ifeq (${DDR_ECC_EN},yes)
|
||||
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
|
||||
endif
|
||||
|
||||
# Platform can control the base address for non-volatile storage.
|
||||
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
|
||||
|
||||
ifeq (${WARM_BOOT},yes)
|
||||
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
|
||||
endif
|
||||
|
||||
# Adding Platform files build files
|
||||
# Adding Platform files build files
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
# Adding SoC build info
|
||||
SUPPORTED_BOOT_MODE := flexspi_nor \
|
||||
sd \
|
||||
emmc
|
||||
|
||||
# Adding platform board build info
|
||||
include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
||||
|
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# Adding SoC build info
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include plat/nxp/soc-lx2160a/soc.mk
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Reference in New Issue