Initialize platform for MediaTek mt8192
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
This commit is contained in:
Nina Wu
parent
9935047b20
commit
f85f37d4f7
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@ -19,6 +19,7 @@ Platform Ports
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intel-stratix10
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marvell/index
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mt8183
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mt8192
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nvidia-tegra
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warp7
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imx8
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@ -0,0 +1,21 @@
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MediaTek 8192
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=============
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MediaTek 8192 (MT8192) is a 64-bit ARM SoC introduced by MediaTek in 2020.
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The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
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Cortex-A76 can operate at up to 2.2 GHz.
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Cortex-A55 can operate at up to 2 GHz.
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Boot Sequence
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-------------
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::
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Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
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How to Build
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------------
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8192 DEBUG=1 COREBOOT=1
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_mediatek_calc_core_pos
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_mediatek_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_mediatek_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
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*
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* In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
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* AFF0 is thread id. There is only one cluster in ARMv8.2
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* and one thread in current implementation.
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*
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* With this function: CorePos = CoreID (AFF1)
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* we do it with x0 = (x0 >> 8) & 0xff
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* -----------------------------------------------------
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*/
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func plat_mediatek_calc_core_pos
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_mediatek_calc_core_pos
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@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Project Includes */
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/* Platform Includes */
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#include <platform_def.h>
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/* Table of regions to map using the MMU. */
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const mmap_region_t plat_mmap[] = {
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/* for TF text, RO, RW */
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MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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/*******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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void plat_configure_mmu_el3(uintptr_t total_base,
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uintptr_t total_size,
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uintptr_t ro_start,
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uintptr_t ro_limit)
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{
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mmap_add_region(total_base, total_base, total_size,
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MT_RW_DATA | MT_SECURE);
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mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
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MT_CODE | MT_SECURE);
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mmap_add(plat_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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@ -0,0 +1,94 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* System Includes */
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#include <assert.h>
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/* Project Includes */
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/coreboot.h>
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/* Platform Includes */
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#include <plat_params.h>
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#include <plat_private.h>
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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assert(next_image_info->h.type == PARAM_EP);
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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* are lost (potentially). This needs to be done before the MMU is initialized
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* so that the memory layout can be used while creating page tables.
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* BL2 has flushed this information to memory, so we are guaranteed to pick up
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* good data.
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******************************************************************************/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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params_early_setup(arg1);
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#if COREBOOT
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if (coreboot_serial.type) {
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console_16550_register(coreboot_serial.baseaddr,
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coreboot_serial.input_hertz,
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coreboot_serial.baud,
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&console);
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}
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#else
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console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
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#endif
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NOTICE("MT8192 bl31_setup\n");
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bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
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}
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/*******************************************************************************
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* Perform any BL31 platform setup code
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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plat_configure_mmu_el3(BL31_START,
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BL31_END - BL31_START,
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BL_CODE_BASE,
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BL_CODE_END);
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_HELPERS_H__
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#define __PLAT_HELPERS_H__
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unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
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#endif /* __PLAT_HELPERS_H__ */
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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* The below macro prints out relevant GIC and
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* CCI registers whenever an unhandled exception
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* is taken in BL31.
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* Clobbers: x0 - x10, x26, x27, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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/* To-do: GIC owner */
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/* To-do: CCI owner */
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.endm
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#endif /* PLAT_MACROS_S */
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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/*******************************************************************************
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* Function and variable prototypes
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******************************************************************************/
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void plat_configure_mmu_el3(uintptr_t total_base,
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uintptr_t total_size,
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uintptr_t ro_start,
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uintptr_t ro_limit);
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#endif /* PLAT_PRIVATE_H */
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#define PLAT_PRIMARY_CPU 0x0
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#define MT_GIC_BASE 0x0c000000
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#define PLAT_MT_CCI_BASE 0x0c500000
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#define MCUCFG_BASE 0x0c530000
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#define IO_PHYS 0x10000000
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/* Aggregate of all devices for MMU mapping */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x10000000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000)
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#define MTK_DEV_RNG1_SIZE 0x10000000
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#define MTK_DEV_RNG2_BASE 0x0c000000
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#define MTK_DEV_RNG2_SIZE 0x600000
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x01002000)
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#define UART1_BASE (IO_PHYS + 0x01003000)
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#define UART_BAUDRATE 115200
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_MHZ 13
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLATFORM_STACK_SIZE 0x800
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZRAM_BASE 0x54600000
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#define TZRAM_SIZE 0x00030000
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 16
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* common headers */
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#include <lib/psci/psci.h>
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/* mediatek platform specific headers */
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* on. The level and mpidr determine the affinity instance.
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******************************************************************************/
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static const plat_psci_ops_t plat_plat_pm_ops = {
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_plat_pm_ops;
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return 0;
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Project Includes */
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/psci/psci.h>
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/* Platform Includes */
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#include <plat_helpers.h>
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#include <platform_def.h>
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const unsigned char mtk_power_domain_tree_desc[] = {
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/* Number of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* Number of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* Number of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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/*******************************************************************************
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* This function returns the MT8192 default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return mtk_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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if (read_mpidr() & MPIDR_MT_MASK) {
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/* ARMv8.2 arch */
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if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) {
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return -1;
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}
|
||||
return plat_mediatek_calc_core_pos(mpidr);
|
||||
}
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
|
||||
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
|
||||
if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Validate cpu_id by checking whether it represents a CPU in
|
||||
* one of the two clusters present on the platform.
|
||||
*/
|
||||
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return (cpu_id + (cluster_id * 8));
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
MTK_PLAT := plat/mediatek
|
||||
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
|
||||
|
||||
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
||||
-I${MTK_PLAT_SOC}/include/
|
||||
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
plat/common/aarch64/crash_console_helpers.S \
|
||||
plat/common/plat_psci_common.c
|
||||
|
||||
BL31_SOURCES += common/desc_image_load.c \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
lib/bl_aux_params/bl_aux_params.c \
|
||||
lib/cpus/aarch64/cortex_a55.S \
|
||||
lib/cpus/aarch64/cortex_a76.S \
|
||||
plat/common/plat_gicv3.c \
|
||||
${MTK_PLAT}/common/mtk_plat_common.c \
|
||||
${MTK_PLAT}/common/params_setup.c \
|
||||
${MTK_PLAT_SOC}/aarch64/platform_common.c \
|
||||
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
|
||||
${MTK_PLAT_SOC}/bl31_plat_setup.c \
|
||||
${MTK_PLAT_SOC}/plat_pm.c \
|
||||
${MTK_PLAT_SOC}/plat_topology.c
|
||||
|
||||
|
||||
# Configs for A76 and A55
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
USE_COHERENT_MEM := 0
|
||||
CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
# indicate the reset vector address can be programmed
|
||||
PROGRAMMABLE_RESET_ADDRESS := 1
|
||||
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
|
||||
MACH_MT8192 := 1
|
||||
$(eval $(call add_define,MACH_MT8192))
|
||||
|
||||
include lib/coreboot/coreboot.mk
|
||||
|
||||
Loading…
Reference in New Issue