n1sdp: update platform macros for dual-chip setup
N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link for now only dual-chip is supported. A single instance of TF-A runs on master chip which should be aware of slave chip's CPU and memory topology. This patch updates platform macros to include remote chip's information and also ensures that a single version of firmware works for both single and dual-chip setup. Change-Id: I75799fd46dc10527aa99585226099d836c21da70 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
This commit is contained in:
Manish Pandey
parent
34c7af41df
commit
f91a8e4c2c
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@ -17,19 +17,20 @@
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Helper function to calculate the core position.
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* (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) +
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* (CPUId * N1SDP_MAX_PE_PER_CPU) +
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* ThreadId
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* ((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) *
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* N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) +
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* (CPUId * N1SDP_MAX_PE_PER_CPU) + ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) *
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* N1SDP_MAX_PE_PER_CPU) + ThreadId
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* (((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) *
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* N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * N1SDP_MAX_PE_PER_CPU) +
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* ThreadId
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* ------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov x3, x0
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mov x4, x0
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/*
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* The MT bit in MPIDR is always set for n1sdp and the
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@ -37,15 +38,18 @@ func plat_arm_calc_core_pos
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*/
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
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madd x2, x3, x4, x2
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mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x5, #N1SDP_MAX_PE_PER_CPU
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madd x0, x1, x5, x0
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mov x4, #N1SDP_MAX_PE_PER_CPU
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madd x0, x1, x4, x0
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ret
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endfunc plat_arm_calc_core_pos
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@ -27,16 +27,27 @@
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
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/* N1SDP remote chip at 4 TB offset */
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#define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42)
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#define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE
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#define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. The access the complete DDR memory
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* space the physical & virtual address space limits are extended to
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* 40-bits.
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* enabling the ECC bits in DMC620. To access the complete DDR memory
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* along with remote chip's DDR memory, which is at 4 TB offset, physical
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* and virtual address space limits are extended to 43-bits.
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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@ -51,34 +62,36 @@
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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#define PLAT_ARM_MAX_BL31_SIZE 0X20000
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/*******************************************************************************
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* N1SDP topology related constants
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******************************************************************************/
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#define N1SDP_MAX_CPUS_PER_CLUSTER 2
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define N1SDP_MAX_PE_PER_CPU 1
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#define N1SDP_MAX_CPUS_PER_CLUSTER U(2)
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define PLAT_N1SDP_CHIP_COUNT U(2)
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#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2)
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#define N1SDP_MAX_PE_PER_CPU U(1)
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \
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PLAT_ARM_CLUSTER_COUNT * \
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N1SDP_MAX_CPUS_PER_CLUSTER * \
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N1SDP_MAX_PE_PER_CPU)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#define PLAT_ARM_MMAP_ENTRIES 6
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#define MAX_XLAT_TABLES 7
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#define PLAT_ARM_MMAP_ENTRIES 9
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#define MAX_XLAT_TABLES 10
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#define PLATFORM_STACK_SIZE 0x400
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_PWR_LVL 2
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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CSS_IRQ_MHU
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@ -88,17 +101,36 @@
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define N1SDP_DEVICE_BASE (0x08000000)
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#define N1SDP_DEVICE_SIZE (0x48000000)
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define N1SDP_DEVICE_BASE ULL(0x08000000)
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#define N1SDP_DEVICE_SIZE ULL(0x48000000)
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#define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE
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#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \
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ARM_DRAM1_BASE, \
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ARM_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \
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ARM_DRAM1_BASE, \
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ARM_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \
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N1SDP_REMOTE_DEVICE_BASE, \
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N1SDP_REMOTE_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \
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N1SDP_REMOTE_DRAM1_BASE, \
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N1SDP_REMOTE_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \
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N1SDP_REMOTE_DRAM2_BASE, \
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N1SDP_REMOTE_DRAM2_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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@ -74,7 +74,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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* from IOFPGA-DDR3 memory to main DDR4 memory.
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*/
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void dmc_ecc_setup(uint32_t ddr_size_gb)
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void dmc_ecc_setup(uint8_t ddr_size_gb)
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{
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uint64_t dram2_size;
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@ -101,6 +101,38 @@ void dmc_ecc_setup(uint32_t ddr_size_gb)
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void remote_dmc_ecc_setup(uint8_t remote_ddr_size)
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{
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uint64_t remote_dram2_size;
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remote_dram2_size = (remote_ddr_size * 1024UL * 1024UL * 1024UL) -
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N1SDP_REMOTE_DRAM1_SIZE;
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/* multichip setup */
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INFO("Zeroing remote DDR memories\n");
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zero_normalmem((void *)N1SDP_REMOTE_DRAM1_BASE,
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N1SDP_REMOTE_DRAM1_SIZE);
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flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE);
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zero_normalmem((void *)N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size);
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flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size);
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INFO("Enabling ECC on remote DMCs\n");
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
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mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG,
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N1SDP_DMC_MEMC_CMD_CONFIG);
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mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG,
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N1SDP_DMC_MEMC_CMD_CONFIG);
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/* Enable ECC in DMCs */
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mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG,
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N1SDP_DMC_ERR0CTLR0_ECC_EN);
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mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG,
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N1SDP_DMC_ERR0CTLR0_ECC_EN);
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/* Set DMCs to READY state */
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mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
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{
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uint32_t i;
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@ -151,6 +183,10 @@ void bl31_platform_setup(void)
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dmc_ecc_setup(plat_info.local_ddr_size);
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/* Check if remote memory is present */
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if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0))
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remote_dmc_ecc_setup(plat_info.remote_ddr_size);
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ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID,
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N1SDP_SDS_BL33_INFO_OFFSET,
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&bl33_info,
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@ -35,6 +35,18 @@
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#define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708
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#define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708
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/* Remote DMC memory command registers */
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#define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC0_MEMC_CMD_REG
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#define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC1_MEMC_CMD_REG
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/* Remote DMC ERR0CTLR0 registers */
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#define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC0_ERR0CTLR0_REG
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#define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC1_ERR0CTLR0_REG
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/* DMC memory commands */
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#define N1SDP_DMC_MEMC_CMD_CONFIG 0
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#define N1SDP_DMC_MEMC_CMD_READY 3
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -25,6 +25,9 @@ const mmap_region_t plat_arm_mmap[] = {
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N1SDP_MAP_NS_SRAM,
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ARM_MAP_DRAM1,
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ARM_MAP_DRAM2,
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N1SDP_MAP_REMOTE_DEVICE,
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N1SDP_MAP_REMOTE_DRAM1,
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N1SDP_MAP_REMOTE_DRAM2,
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{0}
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -19,7 +19,11 @@ typedef struct n1sdp_topology {
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* indices returned by plat_core_pos_by_mpidr().
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*/
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const unsigned char n1sdp_pd_tree_desc[] = {
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PLAT_N1SDP_CHIP_COUNT,
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PLAT_ARM_CLUSTER_COUNT,
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PLAT_ARM_CLUSTER_COUNT,
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N1SDP_MAX_CPUS_PER_CLUSTER,
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N1SDP_MAX_CPUS_PER_CLUSTER,
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N1SDP_MAX_CPUS_PER_CLUSTER,
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N1SDP_MAX_CPUS_PER_CLUSTER
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};
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@ -52,4 +56,4 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
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0, 1, 2, 3};
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0, 1, 2, 3, 4, 5, 6, 7};
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