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rockchip: rk3399: dram: remove dram_init and dts_timing_receive function 

we can reuse the dram config from loader, so we can remove dram_init()
and dts_timing_receive() funciton in dram.c, add the dram_set_odt_pd()
function to get the odt and auto power down parameter from kernel.

This also removes the dcf_code_init function to allow the system to
actually boot.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Derek Basehore 2016-10-20 20:46:43 -07:00 committed by Xing Zheng
parent bcc2bf0977
commit f91b969c1e
6 changed files with 286 additions and 558 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
plat/rockchip/rk3399/drivers/dram/dcf_code.inc
View File

@ -1,7 +1,7 @@
0x0 ,
0x4f8c120c ,
0x7f8c120c ,
0x0 ,
0x4f8c1210 ,
0x7f8c1210 ,
0x100000 ,
0x1f310019 ,
0x0 ,
@ -27,7 +27,7 @@
0x10 ,
0xd0000000 ,
0x1 ,
0x4f8c120c ,
0x7f8c120c ,
0x100000 ,
0x1f310019 ,
0x0 ,
@ -53,11 +53,11 @@
0x10 ,
0xd0000000 ,
0x1 ,
0x4f8c1210 ,
0x7f8c1210 ,
0x0 ,
0x4f8c1220 ,
0x7f8c1220 ,
0x0 ,
0x4f8c121c ,
0x7f8c121c ,
0x0 ,
0xaf8c120d ,
0x108 ,
@ -69,9 +69,9 @@
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x7f8c1220 ,
0x0 ,
0x4f8c121c ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -85,9 +85,9 @@
0x30 ,
0xd0000000 ,
0x1 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c1220 ,
0x0 ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -101,9 +101,9 @@
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x7f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -116,10 +116,10 @@
0xa0000001 ,
0x18 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c1220 ,
0x0 ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -137,9 +137,9 @@
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x7f8c1220 ,
0x0 ,
0x4f8c121c ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -153,9 +153,9 @@
0x30 ,
0xd0000000 ,
0x1 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c1220 ,
0x0 ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -169,9 +169,9 @@
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x7f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
@ -184,10 +184,10 @@
0xa0000001 ,
0x18 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x7f8c1220 ,
0x0 ,
0x7f8c121c ,
0x0 ,
0xaf8c120d ,
0x40 ,
@ -219,23 +219,21 @@
0x0 ,
0x60000001 ,
0xffffffff ,
0x4f77e200 ,
0x7f77e200 ,
0xffffffff ,
0x4f77e204 ,
0x7f77e204 ,
0xffffffff ,
0x4f77e208 ,
0x7f77e208 ,
0xffffffff ,
0x4f77e20c ,
0x7f77e20c ,
0x70007000 ,
0x4f77e210 ,
0x7f77e210 ,
0x3fffffff ,
0x7f750130 ,
0x0 ,
0x2f310061 ,
0xc0000 ,
0x20000001 ,
0x2f310061 ,
0x0 ,
0x4f310061 ,
0x7f310061 ,
0xc0000 ,
0x1f310065 ,
0xc0000 ,
@ -244,6 +242,22 @@
0xc0000000 ,
0x0 ,
0xaf8c121d ,
0x38 ,
0xd0000000 ,
0xff ,
0x1f7601c5 ,
0x0 ,
0x4f8c1215 ,
0xff00ff ,
0x7f7601c4 ,
0xff ,
0x1f7601c9 ,
0x0 ,
0x4f8c1219 ,
0xff00ff ,
0x7f7601c8 ,
0x0 ,
0xaf8c1221 ,
0x48 ,
0xd0000000 ,
0x0 ,
@ -259,15 +273,13 @@
0x18 ,
0xd0000000 ,
0x80000000 ,
0x2f90000d ,
0x2f8f000d ,
0x0 ,
0x4f8f000d ,
0x0 ,
0x2f8c101d ,
0x350005 ,
0x20000001 ,
0x2f8c101d ,
0x0 ,
0x4f620001 ,
0x7f620001 ,
0x1 ,
0x0 ,
0x4 ,
@ -283,11 +295,11 @@
0x0 ,
0x2f8c1005 ,
0x0 ,
0x4f760041 ,
0x7f760041 ,
0x0 ,
0x2f8c1009 ,
0x0 ,
0x4f760045 ,
0x7f760045 ,
0x10000 ,
0x7f76004c ,
0x18 ,
@ -300,10 +312,8 @@
0x60000001 ,
0x3000100 ,
0x7f76004c ,
0x3e8 ,
0x0 ,
0x20002 ,
0x4f620000 ,
0x7f620000 ,
0x1 ,
0x0 ,
0x1 ,
@ -312,6 +322,18 @@
0x60000001 ,
0x0 ,
0xaf8c121d ,
0x28 ,
0xd0000000 ,
0xff0000 ,
0x2f8c1215 ,
0x0 ,
0x4f7601c5 ,
0xff0000 ,
0x2f8c1219 ,
0x0 ,
0x4f7601c9 ,
0x0 ,
0xaf8c1221 ,
0x48 ,
0xd0000000 ,
0x0 ,
@ -327,7 +349,7 @@
0x18 ,
0xd0000000 ,
0x7fffffff ,
0x1f90000d ,
0x1f8f000d ,
0x0 ,
0x4f8f000d ,
0xfff3ffff ,

520
plat/rockchip/rk3399/drivers/dram/dfs.c
View File

@ -84,104 +84,29 @@ struct rk3399_dram_status {
};
static struct rk3399_dram_status rk3399_dram_status;
static struct ddr_dts_config_timing dts_parameter = {
.available = 0
};
static struct rk3399_sdram_default_config ddr3_default_config = {
.bl = 8,
.ap = 0,
.dramds = 40,
.dramodt = 120,
.burst_ref_cnt = 1,
.zqcsi = 0
};
static struct drv_odt_lp_config ddr3_drv_odt_default_config = {
.ddr3_speed_bin = DDR3_DEFAULT,
.pd_idle = 0,
.sr_idle = 0,
.sr_mc_gate_idle = 0,
.srpd_lite_idle = 0,
.standby_idle = 0,
.ddr3_dll_dis_freq = 300,
.phy_dll_dis_freq = 125,
.odt_dis_freq = 933,
.dram_side_drv = 40,
.dram_side_dq_odt = 120,
.dram_side_ca_odt = 120,
.phy_side_ca_drv = 40,
.phy_side_ck_cs_drv = 40,
.phy_side_dq_drv = 40,
.phy_side_odt = 240,
};
static struct rk3399_sdram_default_config lpddr3_default_config = {
.bl = 8,
.ap = 0,
.dramds = 34,
.dramodt = 240,
.burst_ref_cnt = 1,
.zqcsi = 0
};
static struct drv_odt_lp_config lpddr3_drv_odt_default_config = {
.ddr3_speed_bin = DDR3_DEFAULT,
.pd_idle = 0,
.sr_idle = 0,
.sr_mc_gate_idle = 0,
.srpd_lite_idle = 0,
.standby_idle = 0,
.ddr3_dll_dis_freq = 300,
.phy_dll_dis_freq = 125,
.odt_dis_freq = 666,
.dram_side_drv = 40,
.dram_side_dq_odt = 120,
.dram_side_ca_odt = 120,
.phy_side_ca_drv = 40,
.phy_side_ck_cs_drv = 40,
.phy_side_dq_drv = 40,
.phy_side_odt = 240,
};
static struct rk3399_sdram_default_config lpddr4_default_config = {
.bl = 16,
.ap = 0,
.dramds = 40,
.dramodt = 240,
.caodt = 240,
.burst_ref_cnt = 1,
.zqcsi = 0
};
static struct drv_odt_lp_config lpddr4_drv_odt_default_config = {
.ddr3_speed_bin = DDR3_DEFAULT,
.pd_idle = 0,
.sr_idle = 0,
.sr_mc_gate_idle = 0,
.srpd_lite_idle = 0,
.standby_idle = 0,
.ddr3_dll_dis_freq = 300,
.phy_dll_dis_freq = 125,
.odt_dis_freq = 933,
.dram_side_drv = 60,
.dram_side_dq_odt = 40,
.dram_side_ca_odt = 40,
.phy_side_ca_drv = 40,
.phy_side_ck_cs_drv = 80,
.phy_side_dq_drv = 80,
.phy_side_odt = 60,
};
uint32_t dcf_code[] = {
#include "dcf_code.inc"
};
@ -222,176 +147,79 @@ static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config,
return (cs_cap / die);
}
static void drv_odt_lp_cfg_init(uint32_t dram_type,
struct ddr_dts_config_timing *dts_timing,
static void get_dram_drv_odt_val(uint32_t dram_type,
struct drv_odt_lp_config *drv_config)
{
if ((dts_timing) && (dts_timing->available)) {
drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin;
drv_config->pd_idle = dts_timing->pd_idle;
drv_config->sr_idle = dts_timing->sr_idle;
drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle;
drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle;
drv_config->standby_idle = dts_timing->standby_idle;
drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq;
drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq;
}
uint32_t tmp;
uint32_t mr1_val, mr3_val, mr11_val;
switch (dram_type) {
case DDR3:
if ((dts_timing) && (dts_timing->available)) {
drv_config->odt_dis_freq =
dts_timing->ddr3_odt_dis_freq;
drv_config->dram_side_drv = dts_timing->ddr3_drv;
drv_config->dram_side_dq_odt = dts_timing->ddr3_odt;
drv_config->phy_side_ca_drv =
dts_timing->phy_ddr3_ca_drv;
drv_config->phy_side_ck_cs_drv =
dts_timing->phy_ddr3_ca_drv;
drv_config->phy_side_dq_drv =
dts_timing->phy_ddr3_dq_drv;
drv_config->phy_side_odt = dts_timing->phy_ddr3_odt;
} else {
memcpy(drv_config, &ddr3_drv_odt_default_config,
sizeof(struct drv_odt_lp_config));
}
mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff;
tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1);
if (tmp)
drv_config->dram_side_drv = 34;
else
drv_config->dram_side_drv = 40;
tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) |
((mr1_val >> 7) & 1);
if (tmp == 0)
drv_config->dram_side_dq_odt = 0;
else if (tmp == 1)
drv_config->dram_side_dq_odt = 60;
else if (tmp == 3)
drv_config->dram_side_dq_odt = 40;
else
drv_config->dram_side_dq_odt = 120;
break;
case LPDDR3:
if ((dts_timing) && (dts_timing->available)) {
drv_config->odt_dis_freq =
dts_timing->lpddr3_odt_dis_freq;
drv_config->dram_side_drv = dts_timing->lpddr3_drv;
drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt;
drv_config->phy_side_ca_drv =
dts_timing->phy_lpddr3_ca_drv;
drv_config->phy_side_ck_cs_drv =
dts_timing->phy_lpddr3_ca_drv;
drv_config->phy_side_dq_drv =
dts_timing->phy_lpddr3_dq_drv;
drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt;
mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf;
mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3;
if (mr3_val == 0xb)
drv_config->dram_side_drv = 3448;
else if (mr3_val == 0xa)
drv_config->dram_side_drv = 4048;
else if (mr3_val == 0x9)
drv_config->dram_side_drv = 3440;
else if (mr3_val == 0x4)
drv_config->dram_side_drv = 60;
else if (mr3_val == 0x3)
drv_config->dram_side_drv = 48;
else if (mr3_val == 0x2)
drv_config->dram_side_drv = 40;
else
drv_config->dram_side_drv = 34;
} else {
memcpy(drv_config, &lpddr3_drv_odt_default_config,
sizeof(struct drv_odt_lp_config));
}
if (mr11_val == 1)
drv_config->dram_side_dq_odt = 60;
else if (mr11_val == 2)
drv_config->dram_side_dq_odt = 120;
else if (mr11_val == 0)
drv_config->dram_side_dq_odt = 0;
else
drv_config->dram_side_dq_odt = 240;
break;
case LPDDR4:
default:
if ((dts_timing) && (dts_timing->available)) {
drv_config->odt_dis_freq =
dts_timing->lpddr4_odt_dis_freq;
drv_config->dram_side_drv = dts_timing->lpddr4_drv;
drv_config->dram_side_dq_odt =
dts_timing->lpddr4_dq_odt;
drv_config->dram_side_ca_odt =
dts_timing->lpddr4_ca_odt;
drv_config->phy_side_ca_drv =
dts_timing->phy_lpddr4_ca_drv;
drv_config->phy_side_ck_cs_drv =
dts_timing->phy_lpddr4_ck_cs_drv;
drv_config->phy_side_dq_drv =
dts_timing->phy_lpddr4_dq_drv;
drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt;
} else {
memcpy(drv_config, &lpddr4_drv_odt_default_config,
sizeof(struct drv_odt_lp_config));
}
break;
}
mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7;
mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff;
switch (drv_config->phy_side_ca_drv) {
case 240:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_240;
break;
case 120:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_120;
break;
case 80:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_80;
break;
case 60:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_60;
break;
case 48:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_48;
break;
case 40:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_40;
break;
default:
drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3;
break;
};
if ((mr3_val == 0) || (mr3_val == 7))
drv_config->dram_side_drv = 40;
else
drv_config->dram_side_drv = 240 / mr3_val;
switch (drv_config->phy_side_ck_cs_drv) {
case 240:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240;
break;
case 120:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120;
break;
case 80:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80;
break;
case 60:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60;
break;
case 48:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48;
break;
case 40:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40;
break;
default:
drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3;
break;
}
tmp = mr11_val & 0x7;
if ((tmp == 7) || (tmp == 0))
drv_config->dram_side_dq_odt = 0;
else
drv_config->dram_side_dq_odt = 240 / tmp;
switch (drv_config->phy_side_dq_drv) {
case 240:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_240;
break;
case 120:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_120;
break;
case 80:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_80;
break;
case 60:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_60;
break;
case 48:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_48;
break;
case 40:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_40;
break;
default:
drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3;
break;
}
switch (drv_config->phy_side_odt) {
case 240:
drv_config->phy_side_odt = PHY_DRV_ODT_240;
break;
case 120:
drv_config->phy_side_odt = PHY_DRV_ODT_120;
break;
case 80:
drv_config->phy_side_odt = PHY_DRV_ODT_80;
break;
case 60:
drv_config->phy_side_odt = PHY_DRV_ODT_60;
break;
case 48:
drv_config->phy_side_odt = PHY_DRV_ODT_48;
break;
case 40:
drv_config->phy_side_odt = PHY_DRV_ODT_40;
break;
default:
drv_config->phy_side_odt = PHY_DRV_ODT_34_3;
tmp = (mr11_val >> 4) & 0x7;
if ((tmp == 7) || (tmp == 0))
drv_config->dram_side_ca_odt = 0;
else
drv_config->dram_side_ca_odt = 240 / tmp;
break;
}
}
@ -403,8 +231,7 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config,
uint32_t i, j;
for (i = 0; i < sdram_params->num_channels; i++) {
ptiming_config->dram_info[i].speed_rate =
drv_config->ddr3_speed_bin;
ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT;
ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank;
for (j = 0; j < sdram_params->ch[i].rank; j++) {
ptiming_config->dram_info[i].per_die_capability[j] =
@ -1652,59 +1479,6 @@ static void gen_rk3399_set_odt(uint32_t odt_en)
}
}
static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config,
struct drv_odt_lp_config *drv_config)
{
uint32_t i, drv_odt_val;
for (i = 0; i < timing_config->ch_cnt; i++) {
if (timing_config->dram_type == LPDDR4)
drv_odt_val = drv_config->phy_side_odt |
(PHY_DRV_ODT_Hi_Z << 4) |
(drv_config->phy_side_dq_drv << 8) |
(drv_config->phy_side_dq_drv << 12);
else if (timing_config->dram_type == LPDDR3)
drv_odt_val = PHY_DRV_ODT_Hi_Z |
(drv_config->phy_side_odt << 4) |
(drv_config->phy_side_dq_drv << 8) |
(drv_config->phy_side_dq_drv << 12);
else
drv_odt_val = drv_config->phy_side_odt |
(drv_config->phy_side_odt << 4) |
(drv_config->phy_side_dq_drv << 8) |
(drv_config->phy_side_dq_drv << 12);
/* DQ drv odt set */
mmio_clrsetbits_32(PHY_REG(i, 6), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 134), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 262), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 390), 0xffffff, drv_odt_val);
/* DQS drv odt set */
mmio_clrsetbits_32(PHY_REG(i, 7), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 135), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 263), 0xffffff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 391), 0xffffff, drv_odt_val);
gen_rk3399_set_odt(timing_config->odt);
/* CA drv set */
drv_odt_val = drv_config->phy_side_ca_drv |
(drv_config->phy_side_ca_drv << 4);
mmio_clrsetbits_32(PHY_REG(i, 544), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 672), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 800), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 928), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 937), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 935), 0xff, drv_odt_val);
drv_odt_val = drv_config->phy_side_ck_cs_drv |
(drv_config->phy_side_ck_cs_drv << 4);
mmio_clrsetbits_32(PHY_REG(i, 929), 0xff, drv_odt_val);
mmio_clrsetbits_32(PHY_REG(i, 939), 0xff, drv_odt_val);
}
}
static void gen_rk3399_phy_params(struct timing_related_config *timing_config,
struct drv_odt_lp_config *drv_config,
struct dram_timing_t *pdram_timing,
@ -2076,14 +1850,6 @@ static void enable_dcf(uint32_t dcf_addr)
mmio_setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START);
}
void dcf_code_init(void)
{
memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code));
/* set dcf master secure */
mmio_write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0));
mmio_write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000);
}
static void dcf_start(uint32_t freq, uint32_t index)
{
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
@ -2104,37 +1870,21 @@ static void dcf_start(uint32_t freq, uint32_t index)
enable_dcf(DCF_START_ADDR);
}
static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
static void dram_low_power_config(void)
{
uint32_t tmp, tmp1, i;
uint32_t tmp, i;
uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;
uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;
uint32_t *low_power = &rk3399_dram_status.low_power_stat;
if (dram_type == LPDDR4)
tmp = (lp_config->srpd_lite_idle << 16) |
lp_config->pd_idle;
else
tmp = lp_config->pd_idle;
if (dram_type == DDR3)
tmp1 = (2 << 16) | (0x7 << 8) | 7;
tmp = (2 << 16) | (0x7 << 8);
else
tmp1 = (3 << 16) | (0x7 << 8) | 7;
tmp = (3 << 16) | (0x7 << 8);
*low_power = 0;
for (i = 0; i < ch_cnt; i++) {
mmio_write_32(CTL_REG(i, 102), tmp);
mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff,
(lp_config->sr_mc_gate_idle << 8) |
lp_config->sr_idle);
mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp1);
*low_power |= (7 << (8 * i));
}
for (i = 0; i < ch_cnt; i++)
mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp);
/* standby idle */
mmio_write_32(CIC_BASE + CIC_IDLE_TH, lp_config->standby_idle);
mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008);
if (ch_cnt == 2) {
@ -2142,36 +1892,22 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
(((0x1<<4) | (0x1<<5) | (0x1<<6) |
(0x1<<7)) << 16) |
((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
if (lp_config->standby_idle) {
tmp = 0x002a002a;
*low_power |= (1 << 11);
} else
tmp = 0;
mmio_write_32(CIC_BASE + CIC_CTRL1, tmp);
mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028);
}
mmio_write_32(GRF_BASE + GRF_DDRC0_CON1,
(((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) |
((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
if (lp_config->standby_idle) {
tmp = 0x00150015;
*low_power |= (1 << 3);
} else
tmp = 0;
mmio_write_32(CIC_BASE + CIC_CTRL1, tmp);
mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014);
}
static void dram_related_init(struct ddr_dts_config_timing *dts_timing)
void dram_dfs_init(void)
{
uint32_t trefi0, trefi1;
uint32_t i;
dcf_code_init();
/* get sdram config for os reg */
drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing,
&rk3399_dram_status.drv_odt_lp_cfg);
get_dram_drv_odt_val(sdram_config.dramtype,
&rk3399_dram_status.drv_odt_lp_cfg);
sdram_timing_cfg_init(&rk3399_dram_status.timing_config,
&sdram_config,
&rk3399_dram_status.drv_odt_lp_cfg);
@ -2189,28 +1925,63 @@ static void dram_related_init(struct ddr_dts_config_timing *dts_timing)
}
rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1)
& 0x1] = 0;
dram_low_power_config();
}
/* disable all training by ctl and pi */
for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {
mmio_clrbits_32(CTL_REG(i, 70), (1 << 24) |
(1 << 16) | (1 << 8) | 1);
mmio_clrbits_32(CTL_REG(i, 71), 1);
/*
* arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle
* arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle
* arg2: bit0: if odt en
*/
uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2)
{
struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg;
uint32_t *low_power = &rk3399_dram_status.low_power_stat;
uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i;
mmio_clrbits_32(PI_REG(i, 60), 0x3 << 8);
mmio_clrbits_32(PI_REG(i, 80), (0x3 << 24) | (0x3 << 16));
mmio_clrbits_32(PI_REG(i, 100), 0x3 << 8);
mmio_clrbits_32(PI_REG(i, 124), 0x3 << 16);
dram_type = rk3399_dram_status.timing_config.dram_type;
ch_count = rk3399_dram_status.timing_config.ch_cnt;
lp_cfg->sr_idle = arg0 & 0xff;
lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff;
lp_cfg->standby_idle = (arg0 >> 16) & 0xffff;
lp_cfg->pd_idle = arg1 & 0xfff;
lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff;
rk3399_dram_status.timing_config.odt = arg2 & 0x1;
exit_low_power();
*low_power = 0;
/* pd_idle en */
if (lp_cfg->pd_idle)
*low_power |= ((1 << 0) | (1 << 8));
/* sr_idle en srpd_lite_idle */
if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle)
*low_power |= ((1 << 1) | (1 << 9));
/* sr_mc_gate_idle */
if (lp_cfg->sr_mc_gate_idle)
*low_power |= ((1 << 2) | (1 << 10));
/* standbyidle */
if (lp_cfg->standby_idle) {
if (rk3399_dram_status.timing_config.ch_cnt == 2)
*low_power |= ((1 << 3) | (1 << 11));
else
*low_power |= (1 << 3);
}
/* init drv odt */
if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] <
rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq)
rk3399_dram_status.timing_config.odt = 0;
else
rk3399_dram_status.timing_config.odt = 1;
gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config,
&rk3399_dram_status.drv_odt_lp_cfg);
dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg);
pd_tmp = arg1;
if (dram_type != LPDDR4)
pd_tmp = arg1 & 0xfff;
sr_tmp = arg0 & 0xffff;
for (i = 0; i < ch_count; i++) {
mmio_write_32(CTL_REG(i, 102), pd_tmp);
mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp);
}
mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff);
return 0;
}
static uint32_t prepare_ddr_timing(uint32_t mhz)
@ -2220,16 +1991,13 @@ static uint32_t prepare_ddr_timing(uint32_t mhz)
rk3399_dram_status.timing_config.freq = mhz;
if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq)
if (mhz < 300)
rk3399_dram_status.timing_config.dllbp = 1;
else
rk3399_dram_status.timing_config.dllbp = 0;
if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) {
rk3399_dram_status.timing_config.odt = 0;
} else {
rk3399_dram_status.timing_config.odt = 1;
if (rk3399_dram_status.timing_config.odt == 1)
gen_rk3399_set_odt(1);
}
index = (rk3399_dram_status.current_index + 1) & 0x1;
if (rk3399_dram_status.index_freq[index] == mhz)
@ -2249,7 +2017,6 @@ static uint32_t prepare_ddr_timing(uint32_t mhz)
&dram_timing, index);
rk3399_dram_status.index_freq[index] = mhz;
out:
return index;
}
@ -2281,7 +2048,6 @@ uint32_t ddr_set_rate(uint32_t hz)
index = to_get_clk_index(mhz);
mhz = dpll_rates_table[index].mhz;
low_power = exit_low_power();
index = prepare_ddr_timing(mhz);
if (index > 1)
goto out;
@ -2292,10 +2058,7 @@ uint32_t ddr_set_rate(uint32_t hz)
gen_rk3399_set_odt(0);
rk3399_dram_status.current_index = index;
if (mhz < dts_parameter.auto_pd_dis_freq)
low_power |= rk3399_dram_status.low_power_stat;
low_power = rk3399_dram_status.low_power_stat;
resume_low_power(low_power);
out:
return mhz;
@ -2310,30 +2073,3 @@ uint32_t ddr_round_rate(uint32_t hz)
return dpll_rates_table[index].mhz * 1000 * 1000;
}
uint32_t dts_timing_receive(uint32_t timing, uint32_t index)
{
uint32_t *p = (uint32_t *) &dts_parameter;
static uint32_t receive_nums;
if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) {
p[index] = (uint32_t)timing;
receive_nums++;
} else {
dts_parameter.available = 0;
return -1;
}
/* receive all parameter */
if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) {
dts_parameter.available = 1;
receive_nums = 0;
}
return index;
}
void ddr_dfs_init(void)
{
dram_related_init(&dts_parameter);
}

48
plat/rockchip/rk3399/drivers/dram/dfs.h
View File

@ -48,65 +48,23 @@ struct rk3399_sdram_default_config {
unsigned char zqcsi;
};
struct ddr_dts_config_timing {
unsigned int ddr3_speed_bin;
unsigned int pd_idle;
unsigned int sr_idle;
unsigned int sr_mc_gate_idle;
unsigned int srpd_lite_idle;
unsigned int standby_idle;
unsigned int auto_pd_dis_freq;
unsigned int ddr3_dll_dis_freq;
unsigned int phy_dll_dis_freq;
unsigned int ddr3_odt_dis_freq;
unsigned int ddr3_drv;
unsigned int ddr3_odt;
unsigned int phy_ddr3_ca_drv;
unsigned int phy_ddr3_dq_drv;
unsigned int phy_ddr3_odt;
unsigned int lpddr3_odt_dis_freq;
unsigned int lpddr3_drv;
unsigned int lpddr3_odt;
unsigned int phy_lpddr3_ca_drv;
unsigned int phy_lpddr3_dq_drv;
unsigned int phy_lpddr3_odt;
unsigned int lpddr4_odt_dis_freq;
unsigned int lpddr4_drv;
unsigned int lpddr4_dq_odt;
unsigned int lpddr4_ca_odt;
unsigned int phy_lpddr4_ca_drv;
unsigned int phy_lpddr4_ck_cs_drv;
unsigned int phy_lpddr4_dq_drv;
unsigned int phy_lpddr4_odt;
uint32_t available;
};
struct drv_odt_lp_config {
uint32_t ddr3_speed_bin;
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
uint32_t phy_dll_dis_freq;
uint32_t odt_dis_freq;
uint32_t odt_en;
uint32_t dram_side_drv;
uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt;
uint32_t phy_side_ca_drv;
uint32_t phy_side_ck_cs_drv;
uint32_t phy_side_dq_drv;
uint32_t phy_side_odt;
};
void ddr_dfs_init(void);
uint32_t ddr_set_rate(uint32_t hz);
uint32_t ddr_round_rate(uint32_t hz);
uint32_t ddr_get_rate(void);
void clr_dcf_irq(void);
uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
void dram_dfs_init(void);
#endif

145
plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
View File

@ -266,21 +266,24 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config,
break;
}
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
break;
case 40:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
break;
case 120:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
break;
case 0:
default:
if (timing_config->odt)
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
break;
case 40:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
break;
case 120:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
break;
case 0:
default:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
else
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl);
pdram_timing->mr[3] = 0;
@ -750,18 +753,21 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config,
break;
}
pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr11 = LPDDR3_ODT_60;
break;
case 120:
pdram_timing->mr11 = LPDDR3_ODT_120;
break;
case 240:
default:
pdram_timing->mr11 = LPDDR3_ODT_240;
break;
}
if (timing_config->odt)
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr11 = LPDDR3_ODT_60;
break;
case 120:
pdram_timing->mr11 = LPDDR3_ODT_120;
break;
case 240:
default:
pdram_timing->mr11 = LPDDR3_ODT_240;
break;
}
else
pdram_timing->mr11 = LPDDR3_ODT_DIS;
pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000;
pdram_timing->tinit2 = LPDDR3_TINIT2;
@ -1112,47 +1118,52 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config,
break;
}
pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) {
case 240:
tmp = LPDDR4_DQODT_240;
break;
case 120:
tmp = LPDDR4_DQODT_120;
break;
case 80:
tmp = LPDDR4_DQODT_80;
break;
case 60:
tmp = LPDDR4_DQODT_60;
break;
case 48:
tmp = LPDDR4_DQODT_48;
break;
case 40:
default:
tmp = LPDDR4_DQODT_40;
break;
}
switch (timing_config->caodt) {
case 240:
pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
break;
case 120:
pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
break;
case 80:
pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
break;
case 60:
pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
break;
case 48:
pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
break;
case 40:
default:
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
break;
if (timing_config->odt) {
switch (timing_config->dramodt) {
case 240:
tmp = LPDDR4_DQODT_240;
break;
case 120:
tmp = LPDDR4_DQODT_120;
break;
case 80:
tmp = LPDDR4_DQODT_80;
break;
case 60:
tmp = LPDDR4_DQODT_60;
break;
case 48:
tmp = LPDDR4_DQODT_48;
break;
case 40:
default:
tmp = LPDDR4_DQODT_40;
break;
}
switch (timing_config->caodt) {
case 240:
pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
break;
case 120:
pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
break;
case 80:
pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
break;
case 60:
pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
break;
case 48:
pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
break;
case 40:
default:
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
break;
}
} else {
pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp;
}
pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000;

4
plat/rockchip/rk3399/drivers/soc/soc.c
View File

@ -31,10 +31,11 @@
#include <arch_helpers.h>
#include <debug.h>
#include <delay_timer.h>
#include <dfs.h>
#include <dram.h>
#include <mmio.h>
#include <platform_def.h>
#include <plat_private.h>
#include <dram.h>
#include <rk3399_def.h>
#include <rk3399m0.h>
#include <soc.h>
@ -478,4 +479,5 @@ void plat_rockchip_soc_init(void)
plat_rockchip_gpio_init();
soc_m0_init();
dram_init();
dram_dfs_init();
}

13
plat/rockchip/rk3399/plat_sip_calls.c
View File

@ -44,13 +44,12 @@
#define DRAM_GET_RATE 0x05
#define DRAM_CLR_IRQ 0x06
#define DRAM_SET_PARAM 0x07
#define DRAM_SET_ODT_PD 0x08
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
uint64_t id, uint64_t arg2)
{
switch (id) {
case DRAM_INIT:
ddr_dfs_init();
break;
case DRAM_SET_RATE:
return ddr_set_rate((uint32_t)arg0);
case DRAM_ROUND_RATE:
@ -60,8 +59,8 @@ uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
case DRAM_CLR_IRQ:
clr_dcf_irq();
break;
case DRAM_SET_PARAM:
dts_timing_receive((uint32_t)arg0, (uint32_t)arg1);
case DRAM_SET_ODT_PD:
dram_set_odt_pd(arg0, arg1, arg2);
break;
default:
break;
@ -81,7 +80,7 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
{
switch (smc_fid) {
case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);