From f999faca06e8ff5d6d23a08d844c6a4ad38e3000 Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Tue, 9 Apr 2019 14:45:34 +0100 Subject: [PATCH] Add note about erratum 814220 for A7 On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton --- lib/aarch32/cache_helpers.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/aarch32/cache_helpers.S b/lib/aarch32/cache_helpers.S index 810af0f0d..432a30334 100644 --- a/lib/aarch32/cache_helpers.S +++ b/lib/aarch32/cache_helpers.S @@ -124,7 +124,9 @@ loop3: level_done: add r1, r1, #2 // increment the cache number cmp r3, r1 - dsb sy // ensure completion of previous cache maintenance instruction + // Ensure completion of previous cache maintenance instruction. Note + // this also mitigates erratum 814220 on Cortex-A7 + dsb sy bhi loop1 mov r6, #0