Merge pull request #1478 from antonio-nino-diaz-arm/an/rpi3-improvements
rpi3: A few improvements
This commit is contained in:
Soby Mathew
GitHub
commit
f9d2808a1c
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@ -196,29 +196,19 @@ Then compile TF-A. For a AArch32 kernel, use the following command line:
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CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
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RPI3_BL33_IN_AARCH32=1 \
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BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin \
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all fip
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BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin
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For a AArch64 kernel, use this other command line:
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.. code:: shell
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CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
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BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin \
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all fip
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BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin
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Then, join BL1 and the FIP with the following instructions (replace ``release``
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by ``debug`` if you set the build option ``DEBUG=1``):
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.. code:: shell
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cp build/rpi3/release/bl1.bin bl1.pad.bin
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truncate --size=131072 bl1.pad.bin
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cat bl1.pad.bin build/rpi3/release/fip.bin > armstub8.bin
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The resulting file, ``armstub8.bin``, contains BL1 and the FIP in the place they
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need to be for TF-A to boot correctly. Now, follow the instructions in
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`Setup SD card`_.
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The build system concatenates BL1 and the FIP so that the addresses match the
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ones in the memory map. The resulting file is ``armstub8.bin``, located in the
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build folder (e.g. ``build/rpi3/debug/armstub8.bin``). Now, follow the
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instructions in `Setup SD card`_.
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The following build options are supported:
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@ -20,7 +20,8 @@ BL1_SOURCES += drivers/io/io_fip.c \
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plat/common/aarch64/platform_mp_stack.S \
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plat/rpi3/aarch64/plat_helpers.S \
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plat/rpi3/rpi3_bl1_setup.c \
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plat/rpi3/rpi3_io_storage.c
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plat/rpi3/rpi3_io_storage.c \
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plat/rpi3/rpi3_mbox.c
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BL2_SOURCES += common/desc_image_load.c \
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drivers/io/io_fip.c \
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@ -54,6 +55,26 @@ else
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TF_CFLAGS_aarch64 += -mtune=cortex-a53
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endif
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# Platform Makefile target
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# ------------------------
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RPI3_BL1_PAD_BIN := ${BUILD_PLAT}/bl1_pad.bin
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RPI3_ARMSTUB8_BIN := ${BUILD_PLAT}/armstub8.bin
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# Add new default target when compiling this platform
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all: armstub
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# This target concatenates BL1 and the FIP so that the base addresses match the
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# ones defined in the memory map
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armstub: bl1 fip
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@echo " CAT $@"
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${Q}cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN}
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${Q}truncate --size=131072 ${RPI3_BL1_PAD_BIN}
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${Q}cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN}
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@${ECHO_BLANK_LINE}
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@echo "Built $@ successfully"
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@${ECHO_BLANK_LINE}
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# Build config flags
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# ------------------
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@ -7,6 +7,7 @@
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#include <arch.h>
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <xlat_mmu_helpers.h>
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#include <xlat_tables_defs.h>
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@ -56,6 +57,39 @@ void bl1_plat_arch_setup(void)
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void bl1_platform_setup(void)
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{
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uint32_t __unused rev;
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int __unused rc;
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rc = rpi3_vc_hardware_get_board_revision(&rev);
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if (rc == 0) {
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const char __unused *model, __unused *info;
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switch (rev) {
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case 0xA02082:
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model = "Raspberry Pi 3 Model B";
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info = "(1GB, Sony, UK)";
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break;
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case 0xA22082:
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model = "Raspberry Pi 3 Model B";
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info = "(1GB, Embest, China)";
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break;
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case 0xA020D3:
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model = "Raspberry Pi 3 Model B+";
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info = "(1GB, Sony, UK)";
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break;
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default:
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model = "Unknown";
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info = "(Unknown)";
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ERROR("rpi3: Unknown board revision 0x%08x\n", rev);
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break;
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}
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NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev);
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} else {
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ERROR("rpi3: Unable to detect board revision\n");
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}
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/* Initialise the IO layer and register platform IO devices */
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plat_rpi3_io_setup();
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -17,11 +17,25 @@
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#define RPI3_IO_SIZE ULL(0x01000000)
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/*
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* Serial port (called 'Mini UART' in the BCM docucmentation).
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* ARM <-> VideoCore mailboxes
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*/
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#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
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#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
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#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
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#define RPI3_MBOX_OFFSET ULL(0x0000B880)
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#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET)
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/* VideoCore -> ARM */
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#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
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#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
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#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
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#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
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#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
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/* ARM -> VideoCore */
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#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
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#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
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#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034)
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#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038)
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#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C)
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/* Mailbox status constants */
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#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */
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#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */
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/*
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* Power management, reset controller, watchdog.
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@ -30,11 +44,26 @@
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#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET)
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/* Registers on top of RPI3_PM_BASE. */
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#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
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#define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
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#define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
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/* Watchdog constants */
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#define RPI3_PM_PASSWORD ULL(0x5A000000)
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#define RPI3_PM_RSTC_WRCFG_MASK ULL(0x00000030)
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#define RPI3_PM_RSTC_WRCFG_FULL_RESET ULL(0x00000020)
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#define RPI3_PM_PASSWORD U(0x5A000000)
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#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030)
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#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020)
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/*
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* The RSTS register is used by the VideoCore firmware when booting the
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* Raspberry Pi to know which partition to boot from. The partition value is
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* formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
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* to indicate halt.
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*/
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#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555)
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/*
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* Serial port (called 'Mini UART' in the BCM docucmentation).
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*/
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#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
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#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
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#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
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/*
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* Local interrupt controller
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@ -0,0 +1,146 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include "rpi3_hw.h"
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/* This struct must be aligned to 16 bytes */
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typedef struct __packed __aligned(16) rpi3_mbox_request {
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uint32_t size; /* Buffer size in bytes */
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uint32_t code; /* Request/response code */
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uint32_t tags[0];
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} rpi3_mbox_request_t;
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#define RPI3_MBOX_BUFFER_SIZE U(256)
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static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE];
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/* Constants to perform a request/check the status of a request. */
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#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000)
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#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000)
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#define RPI3_MBOX_REQUEST_ERROR U(0x80000001)
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/* Command constants */
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#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002)
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#define RPI3_TAG_END U(0x00000000)
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#define RPI3_TAG_REQUEST U(0x00000000)
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#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */
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#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF)
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#define RPI3_CHANNEL_ARM_TO_VC U(0x8)
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#define RPI3_CHANNEL_MASK U(0xF)
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#define RPI3_MAILBOX_MAX_RETRIES U(1000000)
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/*******************************************************************************
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* Helpers to send requests to the VideoCore using the mailboxes.
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******************************************************************************/
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static void rpi3_vc_mailbox_request_send(void)
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{
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uint32_t st, data;
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uintptr_t resp_addr, addr;
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unsigned int retries;
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/* This is the location of the request buffer */
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addr = (uintptr_t) &rpi3_mbox_buffer;
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/* Make sure that the changes are seen by the VideoCore */
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flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE);
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/* Wait until the outbound mailbox is empty */
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retries = 0U;
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do {
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st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET);
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retries++;
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if (retries == RPI3_MAILBOX_MAX_RETRIES) {
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ERROR("rpi3: mbox: Send request timeout\n");
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return;
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}
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} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U);
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/* Send base address of this message to start request */
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mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET,
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RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr);
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/* Wait until the inbound mailbox isn't empty */
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retries = 0U;
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do {
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st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET);
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retries++;
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if (retries == RPI3_MAILBOX_MAX_RETRIES) {
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ERROR("rpi3: mbox: Receive response timeout\n");
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return;
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}
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} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U);
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/* Get location and channel */
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data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET);
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if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) {
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ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data);
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panic();
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}
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resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK);
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if (addr != resp_addr) {
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ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data);
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panic();
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}
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/* Make sure that the data seen by the CPU is up to date */
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inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE);
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}
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/*******************************************************************************
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* Request board revision. Returns the revision and 0 on success, -1 on error.
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******************************************************************************/
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int rpi3_vc_hardware_get_board_revision(uint32_t *revision)
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{
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uint32_t tag_request_size = sizeof(uint32_t);
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rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer;
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assert(revision != NULL);
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VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req);
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req->size = sizeof(rpi3_mbox_buffer);
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req->code = RPI3_MBOX_PROCESS_REQUEST;
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req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION;
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req->tags[1] = tag_request_size; /* Space available for the response */
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req->tags[2] = RPI3_TAG_REQUEST;
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req->tags[3] = 0; /* Placeholder for the response */
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req->tags[4] = RPI3_TAG_END;
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rpi3_vc_mailbox_request_send();
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if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) {
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ERROR("rpi3: mbox: Code = 0x%08x\n", req->code);
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return -1;
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}
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if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) {
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ERROR("rpi3: mbox: get board revision failed (0x%08x)\n",
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req->tags[2]);
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return -1;
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}
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*revision = req->tags[3];
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return 0;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -150,41 +150,61 @@ void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state)
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}
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/*******************************************************************************
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* Platform handler to reboot the system
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* Platform handlers for system reset and system off.
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******************************************************************************/
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#define RESET_TIMEOUT 10
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static void __dead2 rpi3_system_reset(void)
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/* 10 ticks (Watchdog timer = Timer clock / 16) */
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#define RESET_TIMEOUT U(10)
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static void __dead2 rpi3_watchdog_reset(void)
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{
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/* Setup watchdog for reset */
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static const uintptr_t base = RPI3_PM_BASE;
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uint32_t rstc;
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INFO("rpi3: PSCI System Reset: invoking watchdog reset\n");
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console_flush();
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rstc = mmio_read_32(base + RPI3_PM_RSTC_OFFSET);
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rstc &= ~RPI3_PM_RSTC_WRCFG_MASK;
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rstc |= RPI3_PM_RSTC_WRCFG_FULL_RESET;
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dsbsy();
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isb();
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dmbst();
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/*
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* Watchdog timer = Timer clock / 16
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* Password (31:16) | Value (11:0)
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*/
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mmio_write_32(base + RPI3_PM_WDOG_OFFSET,
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mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET,
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RPI3_PM_PASSWORD | RESET_TIMEOUT);
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mmio_write_32(base + RPI3_PM_RSTC_OFFSET,
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RPI3_PM_PASSWORD | rstc);
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rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET);
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rstc &= ~RPI3_PM_RSTC_WRCFG_MASK;
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rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET;
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mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc);
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for (;;) {
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wfi();
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}
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}
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static void __dead2 rpi3_system_reset(void)
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{
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INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n");
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rpi3_watchdog_reset();
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}
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static void __dead2 rpi3_system_off(void)
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{
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uint32_t rsts;
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INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n");
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/*
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* This function doesn't actually make the Raspberry Pi turn itself off,
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* the hardware doesn't allow it. It simply reboots it and the RSTS
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* value tells the bootcode.bin firmware not to continue the regular
|
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* bootflow and to stay in a low power mode.
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*/
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rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET);
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rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT;
|
||||
mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts);
|
||||
|
||||
rpi3_watchdog_reset();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handlers and setup function.
|
||||
******************************************************************************/
|
||||
|
|
@ -192,6 +212,7 @@ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
|
|||
.cpu_standby = rpi3_cpu_standby,
|
||||
.pwr_domain_on = rpi3_pwr_domain_on,
|
||||
.pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
|
||||
.system_off = rpi3_system_off,
|
||||
.system_reset = rpi3_system_reset,
|
||||
.validate_power_state = rpi3_validate_power_state,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,4 +33,7 @@ uint32_t rpi3_get_spsr_for_bl33_entry(void);
|
|||
/* IO storage utility functions */
|
||||
void plat_rpi3_io_setup(void);
|
||||
|
||||
/* VideoCore firmware commands */
|
||||
int rpi3_vc_hardware_get_board_revision(uint32_t *revision);
|
||||
|
||||
#endif /*__RPI3_PRIVATE_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue