mediatek: mt8183: add MTK uart driver for controlling clock gate
Add uart clock gate contol for suspend/resume scenario. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a
This commit is contained in:
kenny liang
parent
e419574e85
commit
f9f84f44fb
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@ -0,0 +1,111 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <uart.h>
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static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS];
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static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
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UART0_BASE,
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UART1_BASE
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};
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void mt_uart_restore(void)
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{
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int uart_idx = UART_PORT0;
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struct mt_uart *uart;
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unsigned long base;
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/* Must NOT print any debug log before UART restore */
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for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
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uart_idx++) {
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uart = &uart_save_addr[uart_idx];
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base = uart->base;
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mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
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mmio_write_32(UART_EFR(base), uart->registers.efr);
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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mmio_write_32(UART_FCR(base), uart->registers.fcr);
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/* baudrate */
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mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed);
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mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l);
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mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m);
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mmio_write_32(UART_LCR(base),
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uart->registers.lcr | UART_LCR_DLAB);
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mmio_write_32(UART_DLL(base), uart->registers.dll);
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mmio_write_32(UART_DLH(base), uart->registers.dlh);
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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mmio_write_32(UART_SAMPLE_COUNT(base),
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uart->registers.sample_count);
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mmio_write_32(UART_SAMPLE_POINT(base),
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uart->registers.sample_point);
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mmio_write_32(UART_GUARD(base), uart->registers.guard);
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/* flow control */
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mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en);
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mmio_write_32(UART_MCR(base), uart->registers.mcr);
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mmio_write_32(UART_IER(base), uart->registers.ier);
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mmio_write_32(UART_SCR(base), uart->registers.scr);
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}
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}
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void mt_uart_save(void)
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{
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int uart_idx = UART_PORT0;
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struct mt_uart *uart;
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unsigned long base;
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for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
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uart_idx++) {
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uart_save_addr[uart_idx].base = uart_base_addr[uart_idx];
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base = uart_base_addr[uart_idx];
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uart = &uart_save_addr[uart_idx];
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uart->registers.lcr = mmio_read_32(UART_LCR(base));
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mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
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uart->registers.efr = mmio_read_32(UART_EFR(base));
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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uart->registers.fcr = mmio_read_32(UART_FCR_RD(base));
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/* baudrate */
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uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base));
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uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base));
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uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base));
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mmio_write_32(UART_LCR(base),
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uart->registers.lcr | UART_LCR_DLAB);
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uart->registers.dll = mmio_read_32(UART_DLL(base));
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uart->registers.dlh = mmio_read_32(UART_DLH(base));
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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uart->registers.sample_count = mmio_read_32(
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UART_SAMPLE_COUNT(base));
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uart->registers.sample_point = mmio_read_32(
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UART_SAMPLE_POINT(base));
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uart->registers.guard = mmio_read_32(UART_GUARD(base));
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/* flow control */
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uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base));
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uart->registers.mcr = mmio_read_32(UART_MCR(base));
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uart->registers.ier = mmio_read_32(UART_IER(base));
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uart->registers.scr = mmio_read_32(UART_SCR(base));
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}
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}
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void mt_console_uart_cg(int on)
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{
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if (on)
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mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT);
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else
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mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT);
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}
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int mt_console_uart_cg_status(void)
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{
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return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT;
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}
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@ -0,0 +1,100 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __UART_H__
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#define __UART_H__
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#include <platform_def.h>
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/* UART HW information */
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#define HW_SUPPORT_UART_PORTS 2
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#define DRV_SUPPORT_UART_PORTS 2
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/* console UART clock cg */
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#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
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#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
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#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
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#define UART0_CLOCK_GATE_BIT (1U<<22)
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#define UART1_CLOCK_GATE_BIT (1U<<23)
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/* UART registers */
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#define UART_RBR(_baseaddr) (_baseaddr + 0x0)
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#define UART_THR(_baseaddr) (_baseaddr + 0x0)
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#define UART_IER(_baseaddr) (_baseaddr + 0x4)
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#define UART_IIR(_baseaddr) (_baseaddr + 0x8)
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#define UART_FCR(_baseaddr) (_baseaddr + 0x8)
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#define UART_LCR(_baseaddr) (_baseaddr + 0xc)
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#define UART_MCR(_baseaddr) (_baseaddr + 0x10)
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#define UART_LSR(_baseaddr) (_baseaddr + 0x14)
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#define UART_MSR(_baseaddr) (_baseaddr + 0x18)
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#define UART_SCR(_baseaddr) (_baseaddr + 0x1c)
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#define UART_DLL(_baseaddr) (_baseaddr + 0x0)
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#define UART_DLH(_baseaddr) (_baseaddr + 0x4)
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#define UART_EFR(_baseaddr) (_baseaddr + 0x8)
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#define UART_XON1(_baseaddr) (_baseaddr + 0x10)
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#define UART_XON2(_baseaddr) (_baseaddr + 0x14)
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#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18)
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#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c)
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#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20)
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#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24)
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#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28)
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#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c)
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#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30)
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#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34)
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#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38)
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#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c)
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#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40)
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#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44)
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#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48)
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#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c)
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#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50)
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#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54)
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#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58)
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#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C)
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#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0)
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#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4)
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#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8)
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#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC)
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#define UART_LCR_DLAB 0x0080
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#define UART_LCR_MODE_B 0x00bf
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enum uart_port_ID {
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UART_PORT0 = 0,
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UART_PORT1
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};
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struct mt_uart_register {
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unsigned int dll;
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unsigned int dlh;
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unsigned int ier;
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unsigned int lcr;
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unsigned int mcr;
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unsigned int fcr;
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unsigned int lsr;
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unsigned int scr;
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unsigned int efr;
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unsigned int highspeed;
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unsigned int sample_count;
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unsigned int sample_point;
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unsigned int fracdiv_l;
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unsigned int fracdiv_m;
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unsigned int escape_en;
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unsigned int guard;
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unsigned int rx_sel;
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};
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struct mt_uart {
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unsigned long base;
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struct mt_uart_register registers;
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};
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/* external API */
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void mt_uart_save(void);
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void mt_uart_restore(void);
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void mt_console_uart_cg(int on);
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int mt_console_uart_cg_status(void);
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#endif /* __UART_H__ */
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@ -87,6 +87,7 @@
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x01002000)
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#define UART1_BASE (IO_PHYS + 0x01003000)
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#define UART_BAUDRATE 115200
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#define UART_CLOCK 26000000
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@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT_SOC}/drivers/gpio/ \
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-I${MTK_PLAT_SOC}/drivers/pmic/ \
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-I${MTK_PLAT_SOC}/drivers/rtc/ \
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-I${MTK_PLAT_SOC}/drivers/uart/ \
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-I${MTK_PLAT_SOC}/include/
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PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
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@ -47,6 +48,7 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
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${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
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${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
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${MTK_PLAT_SOC}/drivers/uart/uart.c \
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${MTK_PLAT_SOC}/plat_pm.c \
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${MTK_PLAT_SOC}/plat_topology.c \
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${MTK_PLAT_SOC}/plat_mt_gic.c \
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