Merge pull request #614 from soby-mathew/sm/rem_fvp_ve_memmap
FVP: Remove VE memory map support and change default GIC driver
This commit is contained in:
commit
fa7d172b0c
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@ -482,11 +482,10 @@ map is explained in the [Firmware Design].
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* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options:
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* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options:
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- `FVP_GICV2` : The GICv2 only driver is selected
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- `FVP_GICV2` : The GICv2 only driver is selected
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- `FVP_GICV3` : The GICv3 only driver is selected (default option)
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- `FVP_GICV3` : The GICv3 only driver is selected (default option)
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- `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated).
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- `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated)
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Note: If Trusted Firmware is compiled with this option on FVPs with
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Note that if the FVP is configured for legacy VE memory map, then ARM
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GICv3 hardware, then it configures the hardware to run in GICv2
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Trusted Firmware must be compiled with GICv2 only driver using
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emulation mode
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`FVP_USE_GIC_DRIVER=FVP_GICV2` build option.
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* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to
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* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to
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build the topology tree within Trusted Firmware. By default the
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build the topology tree within Trusted Firmware. By default the
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@ -1014,30 +1013,22 @@ all FDTs are available from there.
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* `fvp-base-gicv2-psci.dtb`
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* `fvp-base-gicv2-psci.dtb`
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(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
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For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
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Base memory map configuration.
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Base memory map configuration.
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* `fvp-base-gicv2legacy-psci.dtb`
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For use with AEMv8 Base FVP with legacy VE GIC memory map configuration.
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* `fvp-base-gicv3-psci.dtb`
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* `fvp-base-gicv3-psci.dtb`
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For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map
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(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
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configuration and Linux GICv3 support.
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memory map configuration and Linux GICv3 support.
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* `fvp-foundation-gicv2-psci.dtb`
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* `fvp-foundation-gicv2-psci.dtb`
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(Default) For use with Foundation FVP with Base memory map configuration.
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For use with Foundation FVP with Base memory map configuration.
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* `fvp-foundation-gicv2legacy-psci.dtb`
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For use with Foundation FVP with legacy VE GIC memory map configuration.
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* `fvp-foundation-gicv3-psci.dtb`
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* `fvp-foundation-gicv3-psci.dtb`
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For use with Foundation FVP with Base memory map configuration and Linux
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(Default) For use with Foundation FVP with Base memory map configuration
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GICv3 support.
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and Linux GICv3 support.
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### Running on the Foundation FVP with reset to BL1 entrypoint
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### Running on the Foundation FVP with reset to BL1 entrypoint
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@ -1056,10 +1047,13 @@ The following `Foundation_Platform` parameters should be used to boot Linux with
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--block-device="<path-to>/<file-system-image>"
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--block-device="<path-to>/<file-system-image>"
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Notes:
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Notes:
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* BL1 is loaded at the start of the Trusted ROM.
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* BL1 is loaded at the start of the Trusted ROM.
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* The Firmware Image Package is loaded at the start of NOR FLASH0.
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* The Firmware Image Package is loaded at the start of NOR FLASH0.
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* The Linux kernel image and device tree are loaded in DRAM.
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* The Linux kernel image and device tree are loaded in DRAM.
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* The default use-case for the Foundation FVP is to use the `--gicv3` option
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and enable the GICv3 device in the model. Note that without this option,
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the Foundation FVP defaults to legacy (Versatile Express) memory map which
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is not supported by ARM Trusted Firmware.
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### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
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### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
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@ -1164,88 +1158,6 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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### Configuring the GICv2 memory map
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The Base FVP models support GICv2 with the default model parameters at the
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following addresses. The Foundation FVP also supports these addresses when
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configured for GICv3 in GICv2 emulation mode.
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GICv2 Distributor Interface 0x2f000000
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GICv2 CPU Interface 0x2c000000
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GICv2 Virtual CPU Interface 0x2c010000
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GICv2 Hypervisor Interface 0x2c02f000
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The AEMv8 Base FVP can be configured to support GICv2 at addresses
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corresponding to the legacy (Versatile Express) memory map as follows. These are
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the default addresses when using the Foundation FVP in GICv2 mode.
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GICv2 Distributor Interface 0x2c001000
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GICv2 CPU Interface 0x2c002000
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GICv2 Virtual CPU Interface 0x2c004000
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GICv2 Hypervisor Interface 0x2c006000
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The choice of memory map is reflected in the build variant field (bits[15:12])
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in the `SYS_ID` register (Offset `0x0`) in the Versatile Express System
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registers memory map (`0x1c010000`).
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* `SYS_ID.Build[15:12]`
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`0x1` corresponds to the presence of the Base GIC memory map. This is the
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default value on the Base FVPs.
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* `SYS_ID.Build[15:12]`
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`0x0` corresponds to the presence of the Legacy VE GIC memory map. This is
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the default value on the Foundation FVP.
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This register can be configured as described in the following sections.
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NOTE: If the legacy VE GIC memory map is used, then Trusted Firmware must be
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compiled with the GICv2 only driver, and the corresponding FDT and BL33 images
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should be used.
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#### Configuring AEMv8 Foundation FVP GIC for legacy VE memory map
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The following parameters configure the Foundation FVP to use GICv2 with the
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legacy VE memory map:
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<path-to>/Foundation_Platform \
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--cores=4 \
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--secure-memory \
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--visualization \
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--no-gicv3 \
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--data="<path-to>/<bl1-binary>"@0x0 \
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--data="<path-to>/<FIP-binary>"@0x8000000 \
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--block-device="<path-to>/<file-system-image>"
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Explicit configuration of the `SYS_ID` register is not required.
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#### Configuring AEMv8 Base FVP GIC for legacy VE memory map
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The following parameters configure the AEMv8 Base FVP to use GICv2 with the
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legacy VE memory map. They must added to the parameters described in the
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"Running on the AEMv8 Base FVP" section above:
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-C cluster0.gic.GICD-offset=0x1000 \
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-C cluster0.gic.GICC-offset=0x2000 \
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-C cluster0.gic.GICH-offset=0x4000 \
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-C cluster0.gic.GICH-other-CPU-offset=0x5000 \
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-C cluster0.gic.GICV-offset=0x6000 \
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-C cluster0.gic.PERIPH-size=0x8000 \
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-C cluster1.gic.GICD-offset=0x1000 \
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-C cluster1.gic.GICC-offset=0x2000 \
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-C cluster1.gic.GICH-offset=0x4000 \
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-C cluster1.gic.GICH-other-CPU-offset=0x5000 \
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-C cluster1.gic.GICV-offset=0x6000 \
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-C cluster1.gic.PERIPH-size=0x8000 \
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-C gic_distributor.GICD-alias=0x2c001000 \
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-C gicv3.gicv2-only=1 \
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-C bp.variant=0x0
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The `bp.variant` parameter corresponds to the build variant field of the
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`SYS_ID` register. Setting this to `0x0` allows the ARM Trusted Firmware to
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detect the legacy VE memory map while configuring the GIC.
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10. Running the software on Juno
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10. Running the software on Juno
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---------------------------------
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---------------------------------
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Binary file not shown.
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@ -1,331 +0,0 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/memreserve/ 0x80000000 0x00010000;
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/ {
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};
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/ {
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model = "FVP Base";
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compatible = "arm,vfp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU1:cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU2:cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU3:cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU4:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU5:cpu@101 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU6:cpu@102 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU7:cpu@103 {
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||||||
device_type = "cpu";
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compatible = "arm,armv8";
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||||||
reg = <0x0 0x103>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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||||||
next-level-cache = <&L2_0>;
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||||||
};
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||||||
L2_0: l2-cache0 {
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||||||
compatible = "cache";
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|
||||||
};
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||||||
};
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memory@80000000 {
|
|
||||||
device_type = "memory";
|
|
||||||
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
|
||||||
<0x00000008 0x80000000 0 0x80000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
gic: interrupt-controller@2c001000 {
|
|
||||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
|
||||||
#interrupt-cells = <3>;
|
|
||||||
#address-cells = <0>;
|
|
||||||
interrupt-controller;
|
|
||||||
reg = <0x0 0x2c001000 0 0x1000>,
|
|
||||||
<0x0 0x2c002000 0 0x1000>,
|
|
||||||
<0x0 0x2c004000 0 0x2000>,
|
|
||||||
<0x0 0x2c006000 0 0x2000>;
|
|
||||||
interrupts = <1 9 0xf04>;
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
compatible = "arm,armv8-timer";
|
|
||||||
interrupts = <1 13 0xff01>,
|
|
||||||
<1 14 0xff01>,
|
|
||||||
<1 11 0xff01>,
|
|
||||||
<1 10 0xff01>;
|
|
||||||
clock-frequency = <100000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
timer@2a810000 {
|
|
||||||
compatible = "arm,armv7-timer-mem";
|
|
||||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
|
||||||
clock-frequency = <100000000>;
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
frame@2a830000 {
|
|
||||||
frame-number = <1>;
|
|
||||||
interrupts = <0 26 4>;
|
|
||||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
pmu {
|
|
||||||
compatible = "arm,armv8-pmuv3";
|
|
||||||
interrupts = <0 60 4>,
|
|
||||||
<0 61 4>,
|
|
||||||
<0 62 4>,
|
|
||||||
<0 63 4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
smb {
|
|
||||||
compatible = "simple-bus";
|
|
||||||
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
|
||||||
<1 0 0 0x14000000 0x04000000>,
|
|
||||||
<2 0 0 0x18000000 0x04000000>,
|
|
||||||
<3 0 0 0x1c000000 0x04000000>,
|
|
||||||
<4 0 0 0x0c000000 0x04000000>,
|
|
||||||
<5 0 0 0x10000000 0x04000000>;
|
|
||||||
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
interrupt-map-mask = <0 0 63>;
|
|
||||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
|
||||||
<0 0 1 &gic 0 1 4>,
|
|
||||||
<0 0 2 &gic 0 2 4>,
|
|
||||||
<0 0 3 &gic 0 3 4>,
|
|
||||||
<0 0 4 &gic 0 4 4>,
|
|
||||||
<0 0 5 &gic 0 5 4>,
|
|
||||||
<0 0 6 &gic 0 6 4>,
|
|
||||||
<0 0 7 &gic 0 7 4>,
|
|
||||||
<0 0 8 &gic 0 8 4>,
|
|
||||||
<0 0 9 &gic 0 9 4>,
|
|
||||||
<0 0 10 &gic 0 10 4>,
|
|
||||||
<0 0 11 &gic 0 11 4>,
|
|
||||||
<0 0 12 &gic 0 12 4>,
|
|
||||||
<0 0 13 &gic 0 13 4>,
|
|
||||||
<0 0 14 &gic 0 14 4>,
|
|
||||||
<0 0 15 &gic 0 15 4>,
|
|
||||||
<0 0 16 &gic 0 16 4>,
|
|
||||||
<0 0 17 &gic 0 17 4>,
|
|
||||||
<0 0 18 &gic 0 18 4>,
|
|
||||||
<0 0 19 &gic 0 19 4>,
|
|
||||||
<0 0 20 &gic 0 20 4>,
|
|
||||||
<0 0 21 &gic 0 21 4>,
|
|
||||||
<0 0 22 &gic 0 22 4>,
|
|
||||||
<0 0 23 &gic 0 23 4>,
|
|
||||||
<0 0 24 &gic 0 24 4>,
|
|
||||||
<0 0 25 &gic 0 25 4>,
|
|
||||||
<0 0 26 &gic 0 26 4>,
|
|
||||||
<0 0 27 &gic 0 27 4>,
|
|
||||||
<0 0 28 &gic 0 28 4>,
|
|
||||||
<0 0 29 &gic 0 29 4>,
|
|
||||||
<0 0 30 &gic 0 30 4>,
|
|
||||||
<0 0 31 &gic 0 31 4>,
|
|
||||||
<0 0 32 &gic 0 32 4>,
|
|
||||||
<0 0 33 &gic 0 33 4>,
|
|
||||||
<0 0 34 &gic 0 34 4>,
|
|
||||||
<0 0 35 &gic 0 35 4>,
|
|
||||||
<0 0 36 &gic 0 36 4>,
|
|
||||||
<0 0 37 &gic 0 37 4>,
|
|
||||||
<0 0 38 &gic 0 38 4>,
|
|
||||||
<0 0 39 &gic 0 39 4>,
|
|
||||||
<0 0 40 &gic 0 40 4>,
|
|
||||||
<0 0 41 &gic 0 41 4>,
|
|
||||||
<0 0 42 &gic 0 42 4>;
|
|
||||||
|
|
||||||
/include/ "rtsm_ve-motherboard.dtsi"
|
|
||||||
};
|
|
||||||
|
|
||||||
panels {
|
|
||||||
panel@0 {
|
|
||||||
compatible = "panel";
|
|
||||||
mode = "XVGA";
|
|
||||||
refresh = <60>;
|
|
||||||
xres = <1024>;
|
|
||||||
yres = <768>;
|
|
||||||
pixclock = <15748>;
|
|
||||||
left_margin = <152>;
|
|
||||||
right_margin = <48>;
|
|
||||||
upper_margin = <23>;
|
|
||||||
lower_margin = <3>;
|
|
||||||
hsync_len = <104>;
|
|
||||||
vsync_len = <4>;
|
|
||||||
sync = <0>;
|
|
||||||
vmode = "FB_VMODE_NONINTERLACED";
|
|
||||||
tim2 = "TIM2_BCD", "TIM2_IPC";
|
|
||||||
cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
|
|
||||||
caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
|
|
||||||
bpp = <16>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
Binary file not shown.
|
@ -1,257 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* Redistributions of source code must retain the above copyright notice, this
|
|
||||||
* list of conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
*
|
|
||||||
* Neither the name of the ARM nor the names of its contributors may be used
|
|
||||||
* to endorse or promote products derived from this software without specific
|
|
||||||
* prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
||||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
/memreserve/ 0x80000000 0x00010000;
|
|
||||||
|
|
||||||
/ {
|
|
||||||
};
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "FVP Foundation";
|
|
||||||
compatible = "arm,fvp-base", "arm,vexpress";
|
|
||||||
interrupt-parent = <&gic>;
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
|
|
||||||
chosen { };
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &v2m_serial0;
|
|
||||||
serial1 = &v2m_serial1;
|
|
||||||
serial2 = &v2m_serial2;
|
|
||||||
serial3 = &v2m_serial3;
|
|
||||||
};
|
|
||||||
|
|
||||||
psci {
|
|
||||||
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
|
|
||||||
method = "smc";
|
|
||||||
cpu_suspend = <0xc4000001>;
|
|
||||||
cpu_off = <0x84000002>;
|
|
||||||
cpu_on = <0xc4000003>;
|
|
||||||
sys_poweroff = <0x84000008>;
|
|
||||||
sys_reset = <0x84000009>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpus {
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
cpu-map {
|
|
||||||
cluster0 {
|
|
||||||
core0 {
|
|
||||||
cpu = <&CPU0>;
|
|
||||||
};
|
|
||||||
core1 {
|
|
||||||
cpu = <&CPU1>;
|
|
||||||
};
|
|
||||||
core2 {
|
|
||||||
cpu = <&CPU2>;
|
|
||||||
};
|
|
||||||
core3 {
|
|
||||||
cpu = <&CPU3>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
idle-states {
|
|
||||||
entry-method = "arm,psci";
|
|
||||||
|
|
||||||
CPU_SLEEP_0: cpu-sleep-0 {
|
|
||||||
compatible = "arm,idle-state";
|
|
||||||
local-timer-stop;
|
|
||||||
arm,psci-suspend-param = <0x0010000>;
|
|
||||||
entry-latency-us = <40>;
|
|
||||||
exit-latency-us = <100>;
|
|
||||||
min-residency-us = <150>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
|
||||||
compatible = "arm,idle-state";
|
|
||||||
local-timer-stop;
|
|
||||||
arm,psci-suspend-param = <0x1010000>;
|
|
||||||
entry-latency-us = <500>;
|
|
||||||
exit-latency-us = <1000>;
|
|
||||||
min-residency-us = <2500>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU0:cpu@0 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,armv8";
|
|
||||||
reg = <0x0 0x0>;
|
|
||||||
enable-method = "psci";
|
|
||||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU1:cpu@1 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,armv8";
|
|
||||||
reg = <0x0 0x1>;
|
|
||||||
enable-method = "psci";
|
|
||||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU2:cpu@2 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,armv8";
|
|
||||||
reg = <0x0 0x2>;
|
|
||||||
enable-method = "psci";
|
|
||||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU3:cpu@3 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,armv8";
|
|
||||||
reg = <0x0 0x3>;
|
|
||||||
enable-method = "psci";
|
|
||||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
L2_0: l2-cache0 {
|
|
||||||
compatible = "cache";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
memory@80000000 {
|
|
||||||
device_type = "memory";
|
|
||||||
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
|
||||||
<0x00000008 0x80000000 0 0x80000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
gic: interrupt-controller@2c001000 {
|
|
||||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
|
||||||
#interrupt-cells = <3>;
|
|
||||||
#address-cells = <0>;
|
|
||||||
interrupt-controller;
|
|
||||||
reg = <0x0 0x2c001000 0 0x1000>,
|
|
||||||
<0x0 0x2c002000 0 0x1000>,
|
|
||||||
<0x0 0x2c004000 0 0x2000>,
|
|
||||||
<0x0 0x2c006000 0 0x2000>;
|
|
||||||
interrupts = <1 9 0xf04>;
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
compatible = "arm,armv8-timer";
|
|
||||||
interrupts = <1 13 0xff01>,
|
|
||||||
<1 14 0xff01>,
|
|
||||||
<1 11 0xff01>,
|
|
||||||
<1 10 0xff01>;
|
|
||||||
clock-frequency = <100000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
timer@2a810000 {
|
|
||||||
compatible = "arm,armv7-timer-mem";
|
|
||||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
|
||||||
clock-frequency = <100000000>;
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
frame@2a830000 {
|
|
||||||
frame-number = <1>;
|
|
||||||
interrupts = <0 26 4>;
|
|
||||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
pmu {
|
|
||||||
compatible = "arm,armv8-pmuv3";
|
|
||||||
interrupts = <0 60 4>,
|
|
||||||
<0 61 4>,
|
|
||||||
<0 62 4>,
|
|
||||||
<0 63 4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
smb {
|
|
||||||
compatible = "simple-bus";
|
|
||||||
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
|
||||||
<1 0 0 0x14000000 0x04000000>,
|
|
||||||
<2 0 0 0x18000000 0x04000000>,
|
|
||||||
<3 0 0 0x1c000000 0x04000000>,
|
|
||||||
<4 0 0 0x0c000000 0x04000000>,
|
|
||||||
<5 0 0 0x10000000 0x04000000>;
|
|
||||||
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
interrupt-map-mask = <0 0 63>;
|
|
||||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
|
||||||
<0 0 1 &gic 0 1 4>,
|
|
||||||
<0 0 2 &gic 0 2 4>,
|
|
||||||
<0 0 3 &gic 0 3 4>,
|
|
||||||
<0 0 4 &gic 0 4 4>,
|
|
||||||
<0 0 5 &gic 0 5 4>,
|
|
||||||
<0 0 6 &gic 0 6 4>,
|
|
||||||
<0 0 7 &gic 0 7 4>,
|
|
||||||
<0 0 8 &gic 0 8 4>,
|
|
||||||
<0 0 9 &gic 0 9 4>,
|
|
||||||
<0 0 10 &gic 0 10 4>,
|
|
||||||
<0 0 11 &gic 0 11 4>,
|
|
||||||
<0 0 12 &gic 0 12 4>,
|
|
||||||
<0 0 13 &gic 0 13 4>,
|
|
||||||
<0 0 14 &gic 0 14 4>,
|
|
||||||
<0 0 15 &gic 0 15 4>,
|
|
||||||
<0 0 16 &gic 0 16 4>,
|
|
||||||
<0 0 17 &gic 0 17 4>,
|
|
||||||
<0 0 18 &gic 0 18 4>,
|
|
||||||
<0 0 19 &gic 0 19 4>,
|
|
||||||
<0 0 20 &gic 0 20 4>,
|
|
||||||
<0 0 21 &gic 0 21 4>,
|
|
||||||
<0 0 22 &gic 0 22 4>,
|
|
||||||
<0 0 23 &gic 0 23 4>,
|
|
||||||
<0 0 24 &gic 0 24 4>,
|
|
||||||
<0 0 25 &gic 0 25 4>,
|
|
||||||
<0 0 26 &gic 0 26 4>,
|
|
||||||
<0 0 27 &gic 0 27 4>,
|
|
||||||
<0 0 28 &gic 0 28 4>,
|
|
||||||
<0 0 29 &gic 0 29 4>,
|
|
||||||
<0 0 30 &gic 0 30 4>,
|
|
||||||
<0 0 31 &gic 0 31 4>,
|
|
||||||
<0 0 32 &gic 0 32 4>,
|
|
||||||
<0 0 33 &gic 0 33 4>,
|
|
||||||
<0 0 34 &gic 0 34 4>,
|
|
||||||
<0 0 35 &gic 0 35 4>,
|
|
||||||
<0 0 36 &gic 0 36 4>,
|
|
||||||
<0 0 37 &gic 0 37 4>,
|
|
||||||
<0 0 38 &gic 0 38 4>,
|
|
||||||
<0 0 39 &gic 0 39 4>,
|
|
||||||
<0 0 40 &gic 0 40 4>,
|
|
||||||
<0 0 41 &gic 0 41 4>,
|
|
||||||
<0 0 42 &gic 0 42 4>;
|
|
||||||
|
|
||||||
/include/ "fvp-foundation-motherboard.dtsi"
|
|
||||||
};
|
|
||||||
};
|
|
|
@ -37,10 +37,6 @@
|
||||||
#include <v2m_def.h>
|
#include <v2m_def.h>
|
||||||
#include "../fvp_def.h"
|
#include "../fvp_def.h"
|
||||||
|
|
||||||
#if (FVP_USE_GIC_DRIVER == FVP_GICV2)
|
|
||||||
extern gicv2_driver_data_t arm_gic_data;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Defines for GIC Driver build time selection */
|
/* Defines for GIC Driver build time selection */
|
||||||
#define FVP_GICV2 1
|
#define FVP_GICV2 1
|
||||||
#define FVP_GICV3 2
|
#define FVP_GICV3 2
|
||||||
|
@ -159,26 +155,9 @@ void fvp_config_setup(void)
|
||||||
*/
|
*/
|
||||||
switch (bld) {
|
switch (bld) {
|
||||||
case BLD_GIC_VE_MMAP:
|
case BLD_GIC_VE_MMAP:
|
||||||
#if IMAGE_BL31 || IMAGE_BL32
|
ERROR("Legacy Versatile Express memory map for GIC peripheral"
|
||||||
#if FVP_USE_GIC_DRIVER == FVP_GICV2
|
" is not supported\n");
|
||||||
/*
|
|
||||||
* If the FVP implements the VE compatible memory map, then the
|
|
||||||
* GICv2 driver must be included in the build. Update the platform
|
|
||||||
* data with the correct GICv2 base addresses before it is used
|
|
||||||
* to initialise the driver.
|
|
||||||
*
|
|
||||||
* This update of platform data is temporary and will be removed
|
|
||||||
* once VE memory map for FVP is no longer supported by Trusted
|
|
||||||
* Firmware.
|
|
||||||
*/
|
|
||||||
arm_gic_data.gicd_base = VE_GICD_BASE;
|
|
||||||
arm_gic_data.gicc_base = VE_GICC_BASE;
|
|
||||||
|
|
||||||
#else
|
|
||||||
ERROR("Only GICv2 driver supported for VE memory map\n");
|
|
||||||
panic();
|
panic();
|
||||||
#endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */
|
|
||||||
#endif /* __IMAGE_BL31 || IMAGE_BL32__ */
|
|
||||||
break;
|
break;
|
||||||
case BLD_GIC_A53A57_MMAP:
|
case BLD_GIC_A53A57_MMAP:
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -28,8 +28,8 @@
|
||||||
# POSSIBILITY OF SUCH DAMAGE.
|
# POSSIBILITY OF SUCH DAMAGE.
|
||||||
#
|
#
|
||||||
|
|
||||||
# Use the Legacy GICv3 driver on the FVP by default to maintain compatibility.
|
# Use the GICv3 driver on the FVP by default
|
||||||
FVP_USE_GIC_DRIVER := FVP_GICV3_LEGACY
|
FVP_USE_GIC_DRIVER := FVP_GICV3
|
||||||
|
|
||||||
# The FVP platform depends on this macro to build with correct GIC driver.
|
# The FVP platform depends on this macro to build with correct GIC driver.
|
||||||
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
|
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
|
||||||
|
|
|
@ -47,17 +47,12 @@
|
||||||
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
|
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
|
||||||
* interrupts.
|
* interrupts.
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
const unsigned int g0_interrupt_array[] = {
|
static const unsigned int g0_interrupt_array[] = {
|
||||||
PLAT_ARM_G1S_IRQS,
|
PLAT_ARM_G1S_IRQS,
|
||||||
PLAT_ARM_G0_IRQS
|
PLAT_ARM_G0_IRQS
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
static const gicv2_driver_data_t arm_gic_data = {
|
||||||
* Ideally `arm_gic_data` structure definition should be a `const` but it is
|
|
||||||
* kept as modifiable for overwriting with different GICD and GICC base when
|
|
||||||
* running on FVP with VE memory map.
|
|
||||||
*/
|
|
||||||
gicv2_driver_data_t arm_gic_data = {
|
|
||||||
.gicd_base = PLAT_ARM_GICD_BASE,
|
.gicd_base = PLAT_ARM_GICD_BASE,
|
||||||
.gicc_base = PLAT_ARM_GICC_BASE,
|
.gicc_base = PLAT_ARM_GICC_BASE,
|
||||||
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
|
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
|
||||||
|
|
|
@ -45,15 +45,15 @@
|
||||||
#pragma weak plat_arm_gic_pcpu_init
|
#pragma weak plat_arm_gic_pcpu_init
|
||||||
|
|
||||||
/* The GICv3 driver only needs to be initialized in EL3 */
|
/* The GICv3 driver only needs to be initialized in EL3 */
|
||||||
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
/* Array of Group1 secure interrupts to be configured by the gic driver */
|
/* Array of Group1 secure interrupts to be configured by the gic driver */
|
||||||
const unsigned int g1s_interrupt_array[] = {
|
static const unsigned int g1s_interrupt_array[] = {
|
||||||
PLAT_ARM_G1S_IRQS
|
PLAT_ARM_G1S_IRQS
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Array of Group0 interrupts to be configured by the gic driver */
|
/* Array of Group0 interrupts to be configured by the gic driver */
|
||||||
const unsigned int g0_interrupt_array[] = {
|
static const unsigned int g0_interrupt_array[] = {
|
||||||
PLAT_ARM_G0_IRQS
|
PLAT_ARM_G0_IRQS
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -48,7 +48,7 @@
|
||||||
* In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
|
* In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
|
||||||
* 0 interrupts.
|
* 0 interrupts.
|
||||||
*/
|
*/
|
||||||
const unsigned int irq_sec_array[] = {
|
static const unsigned int irq_sec_array[] = {
|
||||||
PLAT_ARM_G0_IRQS,
|
PLAT_ARM_G0_IRQS,
|
||||||
PLAT_ARM_G1S_IRQS
|
PLAT_ARM_G1S_IRQS
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in New Issue