Merge pull request #614 from soby-mathew/sm/rem_fvp_ve_memmap
FVP: Remove VE memory map support and change default GIC driver
This commit is contained in:
commit
fa7d172b0c
|
@ -482,11 +482,10 @@ map is explained in the [Firmware Design].
|
|||
* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options:
|
||||
- `FVP_GICV2` : The GICv2 only driver is selected
|
||||
- `FVP_GICV3` : The GICv3 only driver is selected (default option)
|
||||
- `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated).
|
||||
|
||||
Note that if the FVP is configured for legacy VE memory map, then ARM
|
||||
Trusted Firmware must be compiled with GICv2 only driver using
|
||||
`FVP_USE_GIC_DRIVER=FVP_GICV2` build option.
|
||||
- `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated)
|
||||
Note: If Trusted Firmware is compiled with this option on FVPs with
|
||||
GICv3 hardware, then it configures the hardware to run in GICv2
|
||||
emulation mode
|
||||
|
||||
* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to
|
||||
build the topology tree within Trusted Firmware. By default the
|
||||
|
@ -1014,30 +1013,22 @@ all FDTs are available from there.
|
|||
|
||||
* `fvp-base-gicv2-psci.dtb`
|
||||
|
||||
(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
|
||||
For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
|
||||
Base memory map configuration.
|
||||
|
||||
* `fvp-base-gicv2legacy-psci.dtb`
|
||||
|
||||
For use with AEMv8 Base FVP with legacy VE GIC memory map configuration.
|
||||
|
||||
* `fvp-base-gicv3-psci.dtb`
|
||||
|
||||
For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map
|
||||
configuration and Linux GICv3 support.
|
||||
(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
|
||||
memory map configuration and Linux GICv3 support.
|
||||
|
||||
* `fvp-foundation-gicv2-psci.dtb`
|
||||
|
||||
(Default) For use with Foundation FVP with Base memory map configuration.
|
||||
|
||||
* `fvp-foundation-gicv2legacy-psci.dtb`
|
||||
|
||||
For use with Foundation FVP with legacy VE GIC memory map configuration.
|
||||
For use with Foundation FVP with Base memory map configuration.
|
||||
|
||||
* `fvp-foundation-gicv3-psci.dtb`
|
||||
|
||||
For use with Foundation FVP with Base memory map configuration and Linux
|
||||
GICv3 support.
|
||||
(Default) For use with Foundation FVP with Base memory map configuration
|
||||
and Linux GICv3 support.
|
||||
|
||||
### Running on the Foundation FVP with reset to BL1 entrypoint
|
||||
|
||||
|
@ -1056,10 +1047,13 @@ The following `Foundation_Platform` parameters should be used to boot Linux with
|
|||
--block-device="<path-to>/<file-system-image>"
|
||||
|
||||
Notes:
|
||||
|
||||
* BL1 is loaded at the start of the Trusted ROM.
|
||||
* The Firmware Image Package is loaded at the start of NOR FLASH0.
|
||||
* The Linux kernel image and device tree are loaded in DRAM.
|
||||
* The default use-case for the Foundation FVP is to use the `--gicv3` option
|
||||
and enable the GICv3 device in the model. Note that without this option,
|
||||
the Foundation FVP defaults to legacy (Versatile Express) memory map which
|
||||
is not supported by ARM Trusted Firmware.
|
||||
|
||||
### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
|
||||
|
||||
|
@ -1164,88 +1158,6 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
|
|||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
|
||||
|
||||
### Configuring the GICv2 memory map
|
||||
|
||||
The Base FVP models support GICv2 with the default model parameters at the
|
||||
following addresses. The Foundation FVP also supports these addresses when
|
||||
configured for GICv3 in GICv2 emulation mode.
|
||||
|
||||
GICv2 Distributor Interface 0x2f000000
|
||||
GICv2 CPU Interface 0x2c000000
|
||||
GICv2 Virtual CPU Interface 0x2c010000
|
||||
GICv2 Hypervisor Interface 0x2c02f000
|
||||
|
||||
The AEMv8 Base FVP can be configured to support GICv2 at addresses
|
||||
corresponding to the legacy (Versatile Express) memory map as follows. These are
|
||||
the default addresses when using the Foundation FVP in GICv2 mode.
|
||||
|
||||
GICv2 Distributor Interface 0x2c001000
|
||||
GICv2 CPU Interface 0x2c002000
|
||||
GICv2 Virtual CPU Interface 0x2c004000
|
||||
GICv2 Hypervisor Interface 0x2c006000
|
||||
|
||||
The choice of memory map is reflected in the build variant field (bits[15:12])
|
||||
in the `SYS_ID` register (Offset `0x0`) in the Versatile Express System
|
||||
registers memory map (`0x1c010000`).
|
||||
|
||||
* `SYS_ID.Build[15:12]`
|
||||
|
||||
`0x1` corresponds to the presence of the Base GIC memory map. This is the
|
||||
default value on the Base FVPs.
|
||||
|
||||
* `SYS_ID.Build[15:12]`
|
||||
|
||||
`0x0` corresponds to the presence of the Legacy VE GIC memory map. This is
|
||||
the default value on the Foundation FVP.
|
||||
|
||||
This register can be configured as described in the following sections.
|
||||
|
||||
NOTE: If the legacy VE GIC memory map is used, then Trusted Firmware must be
|
||||
compiled with the GICv2 only driver, and the corresponding FDT and BL33 images
|
||||
should be used.
|
||||
|
||||
#### Configuring AEMv8 Foundation FVP GIC for legacy VE memory map
|
||||
|
||||
The following parameters configure the Foundation FVP to use GICv2 with the
|
||||
legacy VE memory map:
|
||||
|
||||
<path-to>/Foundation_Platform \
|
||||
--cores=4 \
|
||||
--secure-memory \
|
||||
--visualization \
|
||||
--no-gicv3 \
|
||||
--data="<path-to>/<bl1-binary>"@0x0 \
|
||||
--data="<path-to>/<FIP-binary>"@0x8000000 \
|
||||
--block-device="<path-to>/<file-system-image>"
|
||||
|
||||
Explicit configuration of the `SYS_ID` register is not required.
|
||||
|
||||
#### Configuring AEMv8 Base FVP GIC for legacy VE memory map
|
||||
|
||||
The following parameters configure the AEMv8 Base FVP to use GICv2 with the
|
||||
legacy VE memory map. They must added to the parameters described in the
|
||||
"Running on the AEMv8 Base FVP" section above:
|
||||
|
||||
-C cluster0.gic.GICD-offset=0x1000 \
|
||||
-C cluster0.gic.GICC-offset=0x2000 \
|
||||
-C cluster0.gic.GICH-offset=0x4000 \
|
||||
-C cluster0.gic.GICH-other-CPU-offset=0x5000 \
|
||||
-C cluster0.gic.GICV-offset=0x6000 \
|
||||
-C cluster0.gic.PERIPH-size=0x8000 \
|
||||
-C cluster1.gic.GICD-offset=0x1000 \
|
||||
-C cluster1.gic.GICC-offset=0x2000 \
|
||||
-C cluster1.gic.GICH-offset=0x4000 \
|
||||
-C cluster1.gic.GICH-other-CPU-offset=0x5000 \
|
||||
-C cluster1.gic.GICV-offset=0x6000 \
|
||||
-C cluster1.gic.PERIPH-size=0x8000 \
|
||||
-C gic_distributor.GICD-alias=0x2c001000 \
|
||||
-C gicv3.gicv2-only=1 \
|
||||
-C bp.variant=0x0
|
||||
|
||||
The `bp.variant` parameter corresponds to the build variant field of the
|
||||
`SYS_ID` register. Setting this to `0x0` allows the ARM Trusted Firmware to
|
||||
detect the legacy VE memory map while configuring the GIC.
|
||||
|
||||
|
||||
10. Running the software on Juno
|
||||
---------------------------------
|
||||
|
|
Binary file not shown.
|
@ -1,331 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
/ {
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "FVP Base";
|
||||
compatible = "arm,vfp-base", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
|
||||
method = "smc";
|
||||
cpu_suspend = <0xc4000001>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xc4000003>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <40>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU0:cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU1:cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2:cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU3:cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU4:cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU5:cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU6:cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU7:cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
||||
<0x00000008 0x80000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2c001000 0 0x1000>,
|
||||
<0x0 0x2c002000 0 0x1000>,
|
||||
<0x0 0x2c004000 0 0x2000>,
|
||||
<0x0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer@2a810000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||
clock-frequency = <100000000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
frame@2a830000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 26 4>;
|
||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "rtsm_ve-motherboard.dtsi"
|
||||
};
|
||||
|
||||
panels {
|
||||
panel@0 {
|
||||
compatible = "panel";
|
||||
mode = "XVGA";
|
||||
refresh = <60>;
|
||||
xres = <1024>;
|
||||
yres = <768>;
|
||||
pixclock = <15748>;
|
||||
left_margin = <152>;
|
||||
right_margin = <48>;
|
||||
upper_margin = <23>;
|
||||
lower_margin = <3>;
|
||||
hsync_len = <104>;
|
||||
vsync_len = <4>;
|
||||
sync = <0>;
|
||||
vmode = "FB_VMODE_NONINTERLACED";
|
||||
tim2 = "TIM2_BCD", "TIM2_IPC";
|
||||
cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
|
||||
caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
|
||||
bpp = <16>;
|
||||
};
|
||||
};
|
||||
};
|
Binary file not shown.
|
@ -1,257 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of the ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
/ {
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "FVP Foundation";
|
||||
compatible = "arm,fvp-base", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
|
||||
method = "smc";
|
||||
cpu_suspend = <0xc4000001>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xc4000003>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <40>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU0:cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU1:cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2:cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU3:cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
||||
<0x00000008 0x80000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2c001000 0 0x1000>,
|
||||
<0x0 0x2c002000 0 0x1000>,
|
||||
<0x0 0x2c004000 0 0x2000>,
|
||||
<0x0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer@2a810000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||
clock-frequency = <100000000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
frame@2a830000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 26 4>;
|
||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "fvp-foundation-motherboard.dtsi"
|
||||
};
|
||||
};
|
|
@ -37,10 +37,6 @@
|
|||
#include <v2m_def.h>
|
||||
#include "../fvp_def.h"
|
||||
|
||||
#if (FVP_USE_GIC_DRIVER == FVP_GICV2)
|
||||
extern gicv2_driver_data_t arm_gic_data;
|
||||
#endif
|
||||
|
||||
/* Defines for GIC Driver build time selection */
|
||||
#define FVP_GICV2 1
|
||||
#define FVP_GICV3 2
|
||||
|
@ -159,26 +155,9 @@ void fvp_config_setup(void)
|
|||
*/
|
||||
switch (bld) {
|
||||
case BLD_GIC_VE_MMAP:
|
||||
#if IMAGE_BL31 || IMAGE_BL32
|
||||
#if FVP_USE_GIC_DRIVER == FVP_GICV2
|
||||
/*
|
||||
* If the FVP implements the VE compatible memory map, then the
|
||||
* GICv2 driver must be included in the build. Update the platform
|
||||
* data with the correct GICv2 base addresses before it is used
|
||||
* to initialise the driver.
|
||||
*
|
||||
* This update of platform data is temporary and will be removed
|
||||
* once VE memory map for FVP is no longer supported by Trusted
|
||||
* Firmware.
|
||||
*/
|
||||
arm_gic_data.gicd_base = VE_GICD_BASE;
|
||||
arm_gic_data.gicc_base = VE_GICC_BASE;
|
||||
|
||||
#else
|
||||
ERROR("Only GICv2 driver supported for VE memory map\n");
|
||||
ERROR("Legacy Versatile Express memory map for GIC peripheral"
|
||||
" is not supported\n");
|
||||
panic();
|
||||
#endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */
|
||||
#endif /* __IMAGE_BL31 || IMAGE_BL32__ */
|
||||
break;
|
||||
case BLD_GIC_A53A57_MMAP:
|
||||
break;
|
||||
|
|
|
@ -28,8 +28,8 @@
|
|||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
# Use the Legacy GICv3 driver on the FVP by default to maintain compatibility.
|
||||
FVP_USE_GIC_DRIVER := FVP_GICV3_LEGACY
|
||||
# Use the GICv3 driver on the FVP by default
|
||||
FVP_USE_GIC_DRIVER := FVP_GICV3
|
||||
|
||||
# The FVP platform depends on this macro to build with correct GIC driver.
|
||||
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
|
||||
|
|
|
@ -47,17 +47,12 @@
|
|||
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
|
||||
* interrupts.
|
||||
*****************************************************************************/
|
||||
const unsigned int g0_interrupt_array[] = {
|
||||
static const unsigned int g0_interrupt_array[] = {
|
||||
PLAT_ARM_G1S_IRQS,
|
||||
PLAT_ARM_G0_IRQS
|
||||
};
|
||||
|
||||
/*
|
||||
* Ideally `arm_gic_data` structure definition should be a `const` but it is
|
||||
* kept as modifiable for overwriting with different GICD and GICC base when
|
||||
* running on FVP with VE memory map.
|
||||
*/
|
||||
gicv2_driver_data_t arm_gic_data = {
|
||||
static const gicv2_driver_data_t arm_gic_data = {
|
||||
.gicd_base = PLAT_ARM_GICD_BASE,
|
||||
.gicc_base = PLAT_ARM_GICC_BASE,
|
||||
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
|
||||
|
|
|
@ -45,15 +45,15 @@
|
|||
#pragma weak plat_arm_gic_pcpu_init
|
||||
|
||||
/* The GICv3 driver only needs to be initialized in EL3 */
|
||||
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||
|
||||
/* Array of Group1 secure interrupts to be configured by the gic driver */
|
||||
const unsigned int g1s_interrupt_array[] = {
|
||||
static const unsigned int g1s_interrupt_array[] = {
|
||||
PLAT_ARM_G1S_IRQS
|
||||
};
|
||||
|
||||
/* Array of Group0 interrupts to be configured by the gic driver */
|
||||
const unsigned int g0_interrupt_array[] = {
|
||||
static const unsigned int g0_interrupt_array[] = {
|
||||
PLAT_ARM_G0_IRQS
|
||||
};
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
* In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
|
||||
* 0 interrupts.
|
||||
*/
|
||||
const unsigned int irq_sec_array[] = {
|
||||
static const unsigned int irq_sec_array[] = {
|
||||
PLAT_ARM_G0_IRQS,
|
||||
PLAT_ARM_G1S_IRQS
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue