Fix typos in changelog
Change-Id: Icc6fb03abb9b4ef85931b9e3d767b5a9c271b5f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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@ -61,11 +61,11 @@ New Features
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- Introduce RAS handling on AArch64
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- Introduce RAS handling on AArch64
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- Some RAS extensions are mandatory for ARMv8.2 CPUs, with others
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- Some RAS extensions are mandatory for Armv8.2 CPUs, with others
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mandatory for ARMv8.4 CPUs however, all extensions are also optional
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mandatory for Armv8.4 CPUs however, all extensions are also optional
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extensions to the base ARMv8.0 architecture.
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extensions to the base Armv8.0 architecture.
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- The ARMv8 RAS Extensions introduced Standard Error Records which are a
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- The Armv8 RAS Extensions introduced Standard Error Records which are a
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set of standard registers to configure RAS node policy and allow RAS
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set of standard registers to configure RAS node policy and allow RAS
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Nodes to record and expose error information for error handling agents.
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Nodes to record and expose error information for error handling agents.
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@ -126,7 +126,7 @@ New Features
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- Various changes to support Clang linker and assembler
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- Various changes to support Clang linker and assembler
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- The clang assembler/preprocessor is used when Clang is selected however,
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- The clang assembler/preprocessor is used when Clang is selected. However,
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the clang linker is not used because it is unable to link TF-A objects
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the clang linker is not used because it is unable to link TF-A objects
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due to immaturity of clang linker functionality at this time.
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due to immaturity of clang linker functionality at this time.
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@ -213,12 +213,14 @@ New Features
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- Allwinner sun50i_h6
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- Allwinner sun50i_h6
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- NXP ls1043
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- NXP QorIQ LS1043A
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- NXP i.MX8QX
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- NXP i.MX8QX
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- NXP i.MX8QM
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- NXP i.MX8QM
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- NXP i.MX7Solo WaRP7
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- TI K3
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- TI K3
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- Socionext Synquacer SC2A11
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- Socionext Synquacer SC2A11
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