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plat: imx8m: Correct the imr mask reg offset 

The number of gpc imr mask reg & the offset is different
on some SOC, so correct it & replace the magic number with
macro define.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
This commit is contained in:
Jacky Bai 2020-07-22 16:00:50 +08:00 committed by Manish Pandey
parent 9eb1bb63e1
commit fb9212be17
6 changed files with 9 additions and 2 deletions
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2
plat/imx/imx8m/gpc_common.c
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@ -16,7 +16,7 @@
#include <imx8m_psci.h>
#include <plat_imx8.h>
static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, };
static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };
#pragma weak imx_set_cpu_pwr_off
#pragma weak imx_set_cpu_pwr_on

2
plat/imx/imx8m/imx8mm/include/gpc_reg.h
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@ -124,4 +124,6 @@
#define VPU_G2_PGC 0xf00
#define VPU_H1_PGC 0xf40
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mn/include/gpc_reg.h
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@ -106,4 +106,6 @@
#define GPUMIX_PGC 0xdc0
#define DISPMIX_PGC 0xe80
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mp/include/gpc_reg.h
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@ -146,4 +146,6 @@
#define MEDIAMIX_ISPDWP_PGC 0xf80
#define DDRMIX_PGC 0xfc0
#define IRQ_IMR_NUM U(5)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mq/include/gpc_reg.h
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@ -84,4 +84,6 @@
#define MASTER1_MAPPING BIT(1)
#define MASTER2_MAPPING BIT(2)
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

1
plat/imx/imx8m/include/gpc.h
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@ -25,7 +25,6 @@
#define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4)))
#define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2))
#define IRQ_IMR_NUM 4
#define IMR_MASK_ALL 0xffffffff
#define IMX_PD_DOMAIN(name, on) \