From fbd8f6c8414a49883cbdc32277a0f31fdd3d733d Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 1 Apr 2019 15:27:18 +0100 Subject: [PATCH] aarch32: Allow compiling with soft-float toolchain ARMv7 and Cortex-A32(ARMv8/aarch32) uses "arm-linux-gnueabi" toolchain which has both soft-float and hard-float variants and so there could be scenarios where soft-float toolchain is used.Even though TF-A documentation recommends to use hard-float toolchain for aarch32 but there are external projects where we cannot mandate the selection of toolchain and for those projects at least the build should not fail. Current TF-A source fails to build with soft-float toolchain because assembler does not recognizes "vmsr" instruction which is required to enable floating point unit. To avoid this piece of code being compiled with soft-float toolchain add predefined macro guard " __SOFTFP__" exposed by soft-float toolchain. Change-Id: I76ba40906a8d622dcd476dd36ab4d277a925996c Signed-off-by: Manish Pandey --- include/arch/aarch32/el3_common_macros.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 322aed5cd..0bd897814 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -92,9 +92,14 @@ * * FPEXC.EN: Enable access to Advanced SIMD and floating point features * from all exception levels. + * + * __SOFTFP__: Predefined macro exposed by soft-float toolchain. + * ARMv7 and Cortex-A32(ARMv8/aarch32) has both soft-float and + * hard-float variants of toolchain, avoid compiling below code with + * soft-float toolchain as "vmsr" instruction will not be recognized. * --------------------------------------------------------------------- */ -#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) +#if ((ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)) && !(__SOFTFP__) ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) vmsr FPEXC, r0 isb