rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.37. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295
This commit is contained in:
Chiaki Fujii
Marek Vasut
parent
bf881832e8
commit
fbee88fbb0
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@ -90,7 +90,7 @@ static const struct _boardcnf *board_cnf;
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static uint32_t ddr_phyvalid;
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static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
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static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
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static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
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static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
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static uint32_t max_density;
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static uint32_t ddr0800_mul;
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static uint32_t ddr_mul;
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@ -358,15 +358,13 @@ static void pll3_control(uint32_t high)
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if (high) {
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tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
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(brd_clk * ddr_mul) / 2;
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data_mul = (((ddr_mul * tmp_div) - 1) << 24) |
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(brd_clkdiva << 7);
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data_mul = ((ddr_mul * tmp_div) - 1) << 24;
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pll3_mode = 1;
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loop_max = 2;
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} else {
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tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
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(brd_clk * ddr0800_mul) / 2;
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data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) |
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(brd_clkdiva << 7);
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data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
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pll3_mode = 0;
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loop_max = 8;
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}
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@ -2711,8 +2709,8 @@ static void ddr_register_set(void)
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uint32_t tmp;
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for (fspwp = 1; fspwp >= 0; fspwp--) {
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/*MR13,fspwp */
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send_dbcmd(0x0e840d08 | (fspwp << 6));
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/*MR13, fspwp */
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send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
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tmp =
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ddrtbl_getval(_cnf_DDR_PI_REGSET,
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@ -2745,7 +2743,16 @@ static void ddr_register_set(void)
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send_dbcmd(0x0e840e00 | tmp);
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/* MR22 */
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send_dbcmd(0x0e841616);
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/* ZQCAL start */
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send_dbcmd(0x0d84004F);
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/* ZQLAT */
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send_dbcmd(0x0d840051);
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}
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/* MR13, fspwp */
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send_dbcmd(0x0e840d08);
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}
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/* Training handshake functions */
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@ -3038,12 +3045,6 @@ static uint32_t init_ddr(void)
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/* MRS */
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ddr_register_set();
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/* ZQCAL start */
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send_dbcmd(0x0d84004F);
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/* ZQLAT */
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send_dbcmd(0x0d840051);
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/* Thermal sensor setting */
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/* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
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data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
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@ -3478,17 +3479,21 @@ static uint32_t wdqdm_man(void)
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const uint32_t retry_max = 0x10;
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uint32_t ch, ddr_csn, mr14_bkup[4][4];
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
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(mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
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if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
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(prr_product == PRR_PRODUCT_M3N) ||
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(prr_product == PRR_PRODUCT_V3H)) {
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
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(mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
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(DBSC_DBTR(12) & 0xFF) + 1);
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(mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
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} else {
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
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(DBSC_DBTR(12) & 0xFF) + 1);
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(mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
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}
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ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
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ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
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ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
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retry_cnt = 0;
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err = 0;
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@ -5,7 +5,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RCAR_DDR_VERSION "rev.0.36"
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#define RCAR_DDR_VERSION "rev.0.37"
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#define DRAM_CH_CNT 0x04
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#define SLICE_CNT 0x04
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#define CS_CNT 0x02
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@ -104,7 +104,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
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/*044d*/ 0x00000200,
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/*044e*/ 0x01000000,
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/*044f*/ 0x00000200,
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/*0450*/ 0x4041a141,
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/*0450*/ 0x4041a151,
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/*0451*/ 0xc00141a0,
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/*0452*/ 0x0e0100c0,
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/*0453*/ 0x0010000c,
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@ -114,7 +114,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
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/*0456*/ 0x01000000,
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/*0457*/ 0x00000200,
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/*0458*/ 0x00000004,
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/*0459*/ 0x4041a141,
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/*0459*/ 0x4041a151,
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/*045a*/ 0xc00141a0,
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/*045b*/ 0x0e0000c0,
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/*045c*/ 0x0010000c,
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@ -105,7 +105,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
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/*084e*/ 0x00000000,
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/*084f*/ 0x00010000,
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/*0850*/ 0x00000200,
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/*0851*/ 0x4041a141,
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/*0851*/ 0x4041a151,
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/*0852*/ 0xc00141a0,
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/*0853*/ 0x0e0100c0,
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/*0854*/ 0x0010000c,
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@ -115,7 +115,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
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/*0858*/ 0x01000000,
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/*0859*/ 0x00000200,
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/*085a*/ 0x00000004,
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/*085b*/ 0x4041a141,
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/*085b*/ 0x4041a151,
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/*085c*/ 0x0141c0a0,
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/*085d*/ 0x0000c0c0,
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/*085e*/ 0x0e0c000e,
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