Add a generic driver for ARM CCN IP
This patch adds a device driver which can be used to program the following aspects of ARM CCN IP: 1. Specify the mapping between ACE/ACELite/ACELite+DVM/CHI master interfaces and Request nodes. 2. Add and remove master interfaces from the snoop and dvm domains. 3. Place the L3 cache in a given power state. 4. Configuring system adress map and enabling 3 SN striping mode of memory controller operation. Change-Id: I0f665c6a306938e5b66f6a92f8549b529aa8f325
This commit is contained in:
Achin Gupta
parent
e3616819a9
commit
fd6007de64
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <assert.h>
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#include <bakery_lock.h>
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#include <ccn.h>
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#include <debug.h>
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#include <errno.h>
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#include <mmio.h>
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#include "ccn_private.h"
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static const ccn_desc_t *ccn_plat_desc;
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#if IMAGE_BL31
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DEFINE_BAKERY_LOCK(ccn_lock);
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#endif
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/*******************************************************************************
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* This function takes the base address of the CCN's programmer's view (PV), a
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* region ID of one of the 256 regions (0-255) and a register offset within the
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* region. It converts the first two parameters into a base address and uses it
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* to read the register at the offset.
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******************************************************************************/
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static inline unsigned long long ccn_reg_read(uintptr_t periphbase,
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unsigned int region_id,
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unsigned int register_offset)
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{
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uintptr_t region_base;
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assert(periphbase);
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assert(region_id < REGION_ID_LIMIT);
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region_base = periphbase + region_id_to_base(region_id);
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return mmio_read_64(region_base + register_offset);
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}
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/*******************************************************************************
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* This function takes the base address of the CCN's programmer's view (PV), a
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* region ID of one of the 256 regions (0-255), a register offset within the
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* region and a value. It converts the first two parameters into a base address
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* and uses it to write the value in the register at the offset.
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******************************************************************************/
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static inline void ccn_reg_write(uintptr_t periphbase,
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unsigned int region_id,
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unsigned int register_offset,
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unsigned long long value)
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{
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uintptr_t region_base;
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assert(periphbase);
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assert(region_id < REGION_ID_LIMIT);
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region_base = periphbase + region_id_to_base(region_id);
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mmio_write_64(region_base + register_offset, value);
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}
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#if DEBUG
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typedef struct rn_info {
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unsigned char node_desc[MAX_RN_NODES];
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} rn_info_t;
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/*******************************************************************************
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* This function takes the base address of the CCN's programmer's view (PV) and
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* the node ID of a Request Node (RN-D or RN-I). It returns the maximum number
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* of master interfaces resident on that node. This number is equal to the least
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* significant two bits of the node type ID + 1.
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******************************************************************************/
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static unsigned int ccn_get_rni_mcount(uintptr_t periphbase,
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unsigned int rn_id)
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{
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unsigned int rn_type_id;
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/* Use the node id to find the type of RN-I/D node */
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rn_type_id = get_node_type(ccn_reg_read(periphbase,
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rn_id + RNI_REGION_ID_START,
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REGION_ID_OFFSET));
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/* Return the number master interfaces based on node type */
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return rn_type_id_to_master_cnt(rn_type_id);
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}
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/*******************************************************************************
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* This function reads the CCN registers to find the following information about
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* the ACE/ACELite/ACELite+DVM/CHI interfaces resident on the various types of
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* Request Nodes (RN-Fs, RN-Is and RN-Ds) in the system:
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*
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* 1. The total number of such interfaces that this CCN IP supports. This is the
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* cumulative number of interfaces across all Request node types. It is
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* passed back as the return value of this function.
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*
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* 2. The maximum number of interfaces of a type resident on a Request node of
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* one of the three types. This information is populated in the 'info'
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* array provided by the caller as described next.
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*
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* The array has 64 entries. Each entry corresponds to a Request node. The
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* Miscellaneous node's programmer's view has RN-F, RN-I and RN-D ID
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* registers. For each RN-I and RN-D ID indicated as being present in these
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* registers, its identification register (offset 0xFF00) is read. This
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* register specifies the maximum number of master interfaces the node
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* supports. For RN-Fs it is assumed that there can be only a single fully
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* coherent master resident on each node. The counts for each type of node
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* are use to populate the array entry at the index corresponding to the node
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* ID i.e. rn_info[node ID] = <number of master interfaces>
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******************************************************************************/
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static unsigned int ccn_get_rn_master_info(uintptr_t periphbase,
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rn_info_t *info)
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{
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unsigned int num_masters = 0;
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rn_types_t rn_type;
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assert (info);
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for (rn_type = RN_TYPE_RNF; rn_type < NUM_RN_TYPES; rn_type++) {
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unsigned int mn_reg_off, node_id;
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unsigned long long rn_bitmap;
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/*
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* RN-F, RN-I, RN-D node registers in the MN region occupy
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* contiguous 16 byte apart offsets.
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*/
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mn_reg_off = MN_RNF_NODEID_OFFSET + (rn_type << 4);
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rn_bitmap = ccn_reg_read(periphbase, MN_REGION_ID, mn_reg_off);
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FOR_EACH_PRESENT_NODE_ID(node_id, rn_bitmap) {
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unsigned int node_mcount;
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/*
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* A RN-F does not have a node type since it does not
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* export a programmer's interface. It can only have a
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* single fully coherent master residing on it. If the
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* offset of the MN(Miscellaneous Node) register points
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* to a RN-I/D node then the master count is set to the
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* maximum number of master interfaces that can possibly
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* reside on the node.
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*/
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node_mcount = (mn_reg_off == MN_RNF_NODEID_OFFSET ? 1 :
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ccn_get_rni_mcount(periphbase, node_id));
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/*
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* Use this value to increment the maximum possible
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* master interfaces in the system.
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*/
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num_masters += node_mcount;
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/*
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* Update the entry in 'info' for this node ID with
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* the maximum number of masters than can sit on
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* it. This information will be used to validate the
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* node information passed by the platform later.
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*/
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info->node_desc[node_id] = node_mcount;
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}
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}
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return num_masters;
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}
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/*******************************************************************************
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* This function validates parameters passed by the platform (in a debug build).
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* It collects information about the maximum number of master interfaces that:
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* a) the CCN IP can accommodate and
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* b) can exist on each Request node.
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* It compares this with the information provided by the platform to determine
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* the validity of the latter.
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******************************************************************************/
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static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
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{
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unsigned int master_id, num_rn_masters;
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rn_info_t info = { {0} };
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assert(plat_desc);
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assert(plat_desc->periphbase);
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assert(plat_desc->master_to_rn_id_map);
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assert(plat_desc->num_masters);
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assert(plat_desc->num_masters < CCN_MAX_RN_MASTERS);
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/*
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* Find the number and properties of fully coherent, IO coherent and IO
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* coherent + DVM master interfaces
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*/
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num_rn_masters = ccn_get_rn_master_info(plat_desc->periphbase, &info);
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assert(plat_desc->num_masters < num_rn_masters);
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/*
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* Iterate through the Request nodes specified by the platform.
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* Decrement the count of the masters in the 'info' array for each
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* Request node encountered. If the count would drop below 0 then the
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* platform's view of this aspect of CCN configuration is incorrect.
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*/
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for (master_id = 0; master_id < plat_desc->num_masters; master_id++) {
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unsigned int node_id;
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node_id = plat_desc->master_to_rn_id_map[master_id];
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assert(node_id < MAX_RN_NODES);
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assert(info.node_desc[node_id]);
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info.node_desc[node_id]--;
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}
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}
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#endif /* DEBUG */
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/*******************************************************************************
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* This function validates parameters passed by the platform (in a debug build)
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* and initialises its internal data structures. A lock is required to prevent
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* simultaneous CCN operations at runtime (only BL31) to add and remove Request
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* nodes from coherency.
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******************************************************************************/
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void ccn_init(const ccn_desc_t *plat_desc)
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{
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#if DEBUG
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ccn_validate_plat_params(plat_desc);
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#endif
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ccn_plat_desc = plat_desc;
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}
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/*******************************************************************************
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* This function converts a bit map of master interface IDs to a bit map of the
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* Request node IDs that they reside on.
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******************************************************************************/
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static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map)
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{
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unsigned long long rn_id_map = 0;
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unsigned int node_id, iface_id;
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assert(master_map);
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assert(ccn_plat_desc);
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FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, master_map) {
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/* Convert the master ID into the node ID */
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node_id = ccn_plat_desc->master_to_rn_id_map[iface_id];
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/* Set the bit corresponding to this node ID */
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rn_id_map |= (1UL << node_id);
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}
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return rn_id_map;
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}
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/*******************************************************************************
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* This function executes the necessary operations to add or remove Request node
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* IDs specified in the 'rn_id_map' bitmap from the snoop/DVM domains specified
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* in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/HN-I
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* on which the operation should be performed. 'op_reg_offset' specifies the
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* type of operation (add/remove). 'stat_reg_offset' specifies the register
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* which should be polled to determine if the operation has completed or not.
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******************************************************************************/
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static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map,
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unsigned long long hn_id_map,
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unsigned int region_id,
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unsigned int op_reg_offset,
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unsigned int stat_reg_offset)
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{
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unsigned int start_region_id;
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assert(ccn_plat_desc);
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assert(ccn_plat_desc->periphbase);
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#if IMAGE_BL31
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bakery_lock_get(&ccn_lock);
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#endif
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start_region_id = region_id;
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FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) {
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ccn_reg_write(ccn_plat_desc->periphbase,
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start_region_id,
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op_reg_offset,
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rn_id_map);
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}
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start_region_id = region_id;
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FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) {
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WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(start_region_id,
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stat_reg_offset,
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op_reg_offset,
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rn_id_map);
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}
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#if IMAGE_BL31
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bakery_lock_release(&ccn_lock);
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#endif
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}
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/*******************************************************************************
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* This function reads the bitmap of Home nodes on the basis of the
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* 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN)
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* programmer's view. The MN has a register which carries the bitmap of present
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* Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. It calls
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* 'ccn_snoop_dvm_do_op()' with this information to perform the actual
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* operation.
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******************************************************************************/
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static void ccn_snoop_dvm_domain_common(unsigned long long rn_id_map,
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unsigned int hn_op_reg_offset,
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unsigned int hn_stat_reg_offset,
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unsigned int mn_hn_id_reg_offset,
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unsigned int hn_region_id)
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{
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unsigned long long mn_hn_id_map;
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assert(ccn_plat_desc);
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assert(ccn_plat_desc->periphbase);
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mn_hn_id_map = ccn_reg_read(ccn_plat_desc->periphbase,
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MN_REGION_ID,
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mn_hn_id_reg_offset);
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ccn_snoop_dvm_do_op(rn_id_map,
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mn_hn_id_map,
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hn_region_id,
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hn_op_reg_offset,
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hn_stat_reg_offset);
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}
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/*******************************************************************************
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* The following functions provide the boot and runtime API to the platform for
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* adding and removing master interfaces from the snoop/DVM domains. A bitmap of
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* master interfaces IDs is passed as a parameter. It is converted into a bitmap
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* of Request node IDs using the mapping provided by the platform while
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* initialising the driver.
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* For example, consider a dual cluster system where the clusters have values 0
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* & 1 in the affinity level 1 field of their respective MPIDRs. While
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* initialising this driver, the platform provides the mapping between each
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* cluster and the corresponding Request node. To add or remove a cluster from
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* the snoop and dvm domain, the bit position corresponding to the cluster ID
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* should be set in the 'master_iface_map' i.e. to remove both clusters the
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* bitmap would equal 0x11.
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******************************************************************************/
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void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map)
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{
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unsigned long long rn_id_map;
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rn_id_map = ccn_master_to_rn_id_map(master_iface_map);
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ccn_snoop_dvm_domain_common(rn_id_map,
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HNF_SDC_SET_OFFSET,
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HNF_SDC_STAT_OFFSET,
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MN_HNF_NODEID_OFFSET,
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HNF_REGION_ID_START);
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ccn_snoop_dvm_domain_common(rn_id_map,
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MN_DDC_SET_OFF,
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MN_DDC_STAT_OFFSET,
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MN_HNI_NODEID_OFFSET,
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MN_REGION_ID);
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}
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void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map)
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{
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unsigned long long rn_id_map;
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rn_id_map = ccn_master_to_rn_id_map(master_iface_map);
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ccn_snoop_dvm_domain_common(rn_id_map,
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HNF_SDC_CLR_OFFSET,
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HNF_SDC_STAT_OFFSET,
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MN_HNF_NODEID_OFFSET,
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HNF_REGION_ID_START);
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ccn_snoop_dvm_domain_common(rn_id_map,
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MN_DDC_CLR_OFFSET,
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MN_DDC_STAT_OFFSET,
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MN_HNI_NODEID_OFFSET,
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MN_REGION_ID);
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}
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void ccn_enter_dvm_domain(unsigned long long master_iface_map)
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{
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unsigned long long rn_id_map;
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rn_id_map = ccn_master_to_rn_id_map(master_iface_map);
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ccn_snoop_dvm_domain_common(rn_id_map,
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MN_DDC_SET_OFF,
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MN_DDC_STAT_OFFSET,
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MN_HNI_NODEID_OFFSET,
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MN_REGION_ID);
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}
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void ccn_exit_dvm_domain(unsigned long long master_iface_map)
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{
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unsigned long long rn_id_map;
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rn_id_map = ccn_master_to_rn_id_map(master_iface_map);
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ccn_snoop_dvm_domain_common(rn_id_map,
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MN_DDC_CLR_OFFSET,
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MN_DDC_STAT_OFFSET,
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MN_HNI_NODEID_OFFSET,
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MN_REGION_ID);
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}
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/*******************************************************************************
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* This function returns the run mode of all the L3 cache partitions in the
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* system. The state is expected to be one of NO_L3, SF_ONLY, L3_HAM or
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* L3_FAM. Instead of comparing the states reported by all HN-Fs, the state of
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* the first present HN-F node is reported. Since the driver does not export an
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* interface to program them seperately, there is no reason to perform this
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* check. An HN-F could report that the L3 cache is transitioning from one mode
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* to another e.g. HNF_PM_NOL3_2_SFONLY. In this case, the function waits for
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* the transition to complete and reports the final state.
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******************************************************************************/
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unsigned int ccn_get_l3_run_mode(void)
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{
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unsigned long long hnf_pstate_stat;
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assert(ccn_plat_desc);
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assert(ccn_plat_desc->periphbase);
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/*
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* Wait for a L3 cache paritition to enter any run mode. The pstate
|
||||
* parameter is read from an HN-F P-state status register. A non-zero
|
||||
* value in bits[1:0] means that the cache is transitioning to a run
|
||||
* mode.
|
||||
*/
|
||||
do {
|
||||
hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase,
|
||||
HNF_REGION_ID_START,
|
||||
HNF_PSTATE_STAT_OFFSET);
|
||||
} while (hnf_pstate_stat & 0x3);
|
||||
|
||||
return PSTATE_TO_RUN_MODE(hnf_pstate_stat);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function sets the run mode of all the L3 cache partitions in the
|
||||
* system to one of NO_L3, SF_ONLY, L3_HAM or L3_FAM depending upon the state
|
||||
* specified by the 'mode' argument.
|
||||
******************************************************************************/
|
||||
void ccn_set_l3_run_mode(unsigned int mode)
|
||||
{
|
||||
unsigned long long mn_hnf_id_map, hnf_pstate_stat;
|
||||
unsigned int region_id;
|
||||
|
||||
assert(ccn_plat_desc);
|
||||
assert(ccn_plat_desc->periphbase);
|
||||
assert(mode <= CCN_L3_RUN_MODE_FAM);
|
||||
|
||||
mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase,
|
||||
MN_REGION_ID,
|
||||
MN_HNF_NODEID_OFFSET);
|
||||
region_id = HNF_REGION_ID_START;
|
||||
|
||||
/* Program the desired run mode */
|
||||
FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) {
|
||||
ccn_reg_write(ccn_plat_desc->periphbase,
|
||||
region_id,
|
||||
HNF_PSTATE_REQ_OFFSET,
|
||||
mode);
|
||||
}
|
||||
|
||||
/* Wait for the caches to transition to the run mode */
|
||||
region_id = HNF_REGION_ID_START;
|
||||
FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) {
|
||||
/*
|
||||
* Wait for a L3 cache paritition to enter a target run
|
||||
* mode. The pstate parameter is read from an HN-F P-state
|
||||
* status register.
|
||||
*/
|
||||
do {
|
||||
hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase,
|
||||
region_id,
|
||||
HNF_PSTATE_STAT_OFFSET);
|
||||
} while (((hnf_pstate_stat & HNF_PSTATE_MASK) >> 2) != mode);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function configures system address map and provides option to enable the
|
||||
* 3SN striping mode of Slave node operation. The Slave node IDs and the Top
|
||||
* Address bit1 and bit0 are provided as parameters to this function. This
|
||||
* configuration is needed only if network contains a single SN-F or 3 SN-F and
|
||||
* must be completed before the first request by the system to normal memory.
|
||||
******************************************************************************/
|
||||
void ccn_program_sys_addrmap(unsigned int sn0_id,
|
||||
unsigned int sn1_id,
|
||||
unsigned int sn2_id,
|
||||
unsigned int top_addr_bit0,
|
||||
unsigned int top_addr_bit1,
|
||||
unsigned char three_sn_en)
|
||||
{
|
||||
unsigned long long mn_hnf_id_map, hnf_sam_ctrl_value;
|
||||
unsigned int region_id;
|
||||
|
||||
assert(ccn_plat_desc);
|
||||
assert(ccn_plat_desc->periphbase);
|
||||
|
||||
mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase,
|
||||
MN_REGION_ID,
|
||||
MN_HNF_NODEID_OFFSET);
|
||||
region_id = HNF_REGION_ID_START;
|
||||
hnf_sam_ctrl_value = MAKE_HNF_SAM_CTRL_VALUE(sn0_id,
|
||||
sn1_id,
|
||||
sn2_id,
|
||||
top_addr_bit0,
|
||||
top_addr_bit1,
|
||||
three_sn_en);
|
||||
|
||||
FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) {
|
||||
|
||||
/* Program the SAM control register */
|
||||
ccn_reg_write(ccn_plat_desc->periphbase,
|
||||
region_id,
|
||||
HNF_SAM_CTRL_OFFSET,
|
||||
hnf_sam_ctrl_value);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CCN_PRIVATE_H__
|
||||
#define __CCN_PRIVATE_H__
|
||||
|
||||
/*
|
||||
* A CCN implementation can have a maximum of 64 Request nodes with node IDs
|
||||
* from 0-63. These IDs are split across the three types of Request nodes
|
||||
* i.e. RN-F, RN-D and RN-I.
|
||||
*/
|
||||
#define MAX_RN_NODES 64
|
||||
|
||||
/* Enum used to loop through the 3 types of Request nodes */
|
||||
typedef enum rn_types {
|
||||
RN_TYPE_RNF = 0,
|
||||
RN_TYPE_RNI,
|
||||
RN_TYPE_RND,
|
||||
NUM_RN_TYPES
|
||||
} rn_types_t;
|
||||
|
||||
/* Macro to convert a region id to its base address */
|
||||
#define region_id_to_base(id) ((id) << 16)
|
||||
|
||||
/*
|
||||
* Macro to calculate the number of master interfaces resident on a RN-I/RN-D.
|
||||
* Value of first two bits of the RN-I/D node type + 1 == Maximum number of
|
||||
* ACE-Lite or ACE-Lite+DVM interfaces supported on this node. E.g.
|
||||
*
|
||||
* 0x14 : RN-I with 1 ACE-Lite interface
|
||||
* 0x15 : RN-I with 2 ACE-Lite interfaces
|
||||
* 0x16 : RN-I with 3 ACE-Lite interfaces
|
||||
*/
|
||||
#define rn_type_id_to_master_cnt(id) (((id) & 0x3) + 1)
|
||||
|
||||
/*
|
||||
* Constants used to identify a region in the programmer's view. These are
|
||||
* common for all regions.
|
||||
*/
|
||||
#define REGION_ID_LIMIT 256
|
||||
#define REGION_ID_OFFSET 0xFF00
|
||||
|
||||
#define REGION_NODE_ID_SHIFT 8
|
||||
#define REGION_NODE_ID_MASK 0x7f
|
||||
#define get_node_id(id_reg) (((id_reg) >> REGION_NODE_ID_SHIFT) \
|
||||
& REGION_NODE_ID_MASK)
|
||||
|
||||
#define REGION_NODE_TYPE_SHIFT 0
|
||||
#define REGION_NODE_TYPE_MASK 0x1f
|
||||
#define get_node_type(id_reg) (((id_reg) >> REGION_NODE_TYPE_SHIFT) \
|
||||
& REGION_NODE_TYPE_MASK)
|
||||
|
||||
/* Common offsets of registers to enter or exit a snoop/dvm domain */
|
||||
#define DOMAIN_CTRL_STAT_OFFSET 0x0200
|
||||
#define DOMAIN_CTRL_SET_OFFSET 0x0210
|
||||
#define DOMAIN_CTRL_CLR_OFFSET 0x0220
|
||||
|
||||
/*
|
||||
* Thess macros are used to determine if an operation to add or remove a Request
|
||||
* node from the snoop/dvm domain has completed. 'rn_id_map' is a bit map of
|
||||
* nodes. It was used to program the SET or CLEAR control register. The type of
|
||||
* register is specified by 'op_reg_offset'. 'status_reg' is the bit map of
|
||||
* nodes currently present in the snoop/dvm domain. 'rn_id_map' and 'status_reg'
|
||||
* are logically ANDed and the result it stored back in the 'status_reg'. There
|
||||
* are two outcomes of this operation:
|
||||
*
|
||||
* 1. If the DOMAIN_CTRL_SET_OFFSET register was programmed, then the set bits in
|
||||
* 'rn_id_map' should appear in 'status_reg' when the operation completes. So
|
||||
* after the AND operation, at some point of time 'status_reg' should equal
|
||||
* 'rn_id_map'.
|
||||
*
|
||||
* 2. If the DOMAIN_CTRL_CLR_OFFSET register was programmed, then the set bits in
|
||||
* 'rn_id_map' should disappear in 'status_reg' when the operation
|
||||
* completes. So after the AND operation, at some point of time 'status_reg'
|
||||
* should equal 0.
|
||||
*/
|
||||
#define WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(region_id, stat_reg_offset, \
|
||||
op_reg_offset, rn_id_map) \
|
||||
{ \
|
||||
uint64_t status_reg; \
|
||||
do { \
|
||||
status_reg = ccn_reg_read((ccn_plat_desc->periphbase), \
|
||||
(region_id), \
|
||||
(stat_reg_offset)); \
|
||||
status_reg &= (rn_id_map); \
|
||||
} while ((op_reg_offset) == DOMAIN_CTRL_SET_OFFSET ? \
|
||||
(rn_id_map) != status_reg : status_reg); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Region ID of the Miscellaneous Node is always 0 as its located at the base of
|
||||
* the programmer's view.
|
||||
*/
|
||||
#define MN_REGION_ID 0
|
||||
|
||||
#define MN_REGION_ID_START 0
|
||||
#define DEBUG_REGION_ID_START 1
|
||||
#define HNI_REGION_ID_START 8
|
||||
#define SBSX_REGION_ID_START 16
|
||||
#define HNF_REGION_ID_START 32
|
||||
#define XP_REGION_ID_START 64
|
||||
#define RNI_REGION_ID_START 128
|
||||
|
||||
/* Selected register offsets from the base of a HNF region */
|
||||
#define HNF_CFG_CTRL_OFFSET 0x0000
|
||||
#define HNF_SAM_CTRL_OFFSET 0x0008
|
||||
#define HNF_PSTATE_REQ_OFFSET 0x0010
|
||||
#define HNF_PSTATE_STAT_OFFSET 0x0018
|
||||
#define HNF_SDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET
|
||||
#define HNF_SDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET
|
||||
#define HNF_SDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET
|
||||
#define HNF_AUX_CTRL_OFFSET 0x0500
|
||||
|
||||
/* Selected register offsets from the base of a MN region */
|
||||
#define MN_SAR_OFFSET 0x0000
|
||||
#define MN_RNF_NODEID_OFFSET 0x0180
|
||||
#define MN_RNI_NODEID_OFFSET 0x0190
|
||||
#define MN_RND_NODEID_OFFSET 0x01A0
|
||||
#define MN_HNF_NODEID_OFFSET 0x01B0
|
||||
#define MN_HNI_NODEID_OFFSET 0x01C0
|
||||
#define MN_SN_NODEID_OFFSET 0x01D0
|
||||
#define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET
|
||||
#define MN_DDC_SET_OFF DOMAIN_CTRL_SET_OFFSET
|
||||
#define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET
|
||||
#define MN_ID_OFFSET REGION_ID_OFFSET
|
||||
|
||||
/* HNF System Address Map register bit masks and shifts */
|
||||
#define HNF_SAM_CTRL_SN_ID_MASK 0x7f
|
||||
#define HNF_SAM_CTRL_SN0_ID_SHIFT 0
|
||||
#define HNF_SAM_CTRL_SN1_ID_SHIFT 8
|
||||
#define HNF_SAM_CTRL_SN2_ID_SHIFT 16
|
||||
|
||||
#define HNF_SAM_CTRL_TAB0_MASK 0x3fUL
|
||||
#define HNF_SAM_CTRL_TAB0_SHIFT 48
|
||||
#define HNF_SAM_CTRL_TAB1_MASK 0x3fUL
|
||||
#define HNF_SAM_CTRL_TAB1_SHIFT 56
|
||||
|
||||
#define HNF_SAM_CTRL_3SN_ENB_SHIFT 32
|
||||
#define HNF_SAM_CTRL_3SN_ENB_MASK 0x01UL
|
||||
|
||||
/*
|
||||
* Macro to create a value suitable for programming into a HNF SAM Control
|
||||
* register for enabling 3SN striping.
|
||||
*/
|
||||
#define MAKE_HNF_SAM_CTRL_VALUE(sn0, sn1, sn2, tab0, tab1, three_sn_en) \
|
||||
((((sn0) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN0_ID_SHIFT) | \
|
||||
(((sn1) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN1_ID_SHIFT) | \
|
||||
(((sn2) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN2_ID_SHIFT) | \
|
||||
(((tab0) & HNF_SAM_CTRL_TAB0_MASK) << HNF_SAM_CTRL_TAB0_SHIFT) | \
|
||||
(((tab1) & HNF_SAM_CTRL_TAB1_MASK) << HNF_SAM_CTRL_TAB1_SHIFT) | \
|
||||
(((three_sn_en) & HNF_SAM_CTRL_3SN_ENB_MASK) << HNF_SAM_CTRL_3SN_ENB_SHIFT))
|
||||
|
||||
/* Mask to read the power state value from an HN-F P-state register */
|
||||
#define HNF_PSTATE_MASK 0xf
|
||||
|
||||
/* Macro to extract the run mode from a p-state value */
|
||||
#define PSTATE_TO_RUN_MODE(pstate) (((pstate) & HNF_PSTATE_MASK) >> 2)
|
||||
|
||||
/*
|
||||
* Helper macro that iterates through a given bit map. In each iteration,
|
||||
* it returns the position of the set bit.
|
||||
* It can be used by other utility macros to iterates through all nodes
|
||||
* or masters given a bit map of them.
|
||||
*/
|
||||
#define FOR_EACH_BIT(bit_pos, bit_map) \
|
||||
for (bit_pos = __builtin_ctzll(bit_map); \
|
||||
bit_map; \
|
||||
bit_map &= ~(1UL << bit_pos), \
|
||||
bit_pos = __builtin_ctzll(bit_map))
|
||||
|
||||
/*
|
||||
* Utility macro that iterates through a bit map of node IDs. In each
|
||||
* iteration, it returns the ID of the next present node in the bit map. Node
|
||||
* ID of a present node == Position of set bit == Number of zeroes trailing the
|
||||
* bit.
|
||||
*/
|
||||
#define FOR_EACH_PRESENT_NODE_ID(node_id, bit_map) \
|
||||
FOR_EACH_BIT(node_id, bit_map)
|
||||
|
||||
/*
|
||||
* Helper function to return number of set bits in bitmap
|
||||
*/
|
||||
static inline unsigned int count_set_bits(uint64_t bitmap)
|
||||
{
|
||||
unsigned int count = 0;
|
||||
|
||||
for (; bitmap; bitmap &= bitmap - 1)
|
||||
++count;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/*
|
||||
* Utility macro that iterates through a bit map of node IDs. In each iteration,
|
||||
* it returns the ID of the next present region corresponding to a node present
|
||||
* in the bit map. Region ID of a present node is in between passed region id
|
||||
* and region id + number of set bits in the bitmap i.e. the number of present
|
||||
* nodes.
|
||||
*/
|
||||
#define FOR_EACH_PRESENT_REGION_ID(region_id, bit_map) \
|
||||
for (unsigned long long region_id_limit = count_set_bits(bit_map) \
|
||||
+ region_id; \
|
||||
region_id < region_id_limit; \
|
||||
region_id++)
|
||||
|
||||
/*
|
||||
* Same macro as FOR_EACH_PRESENT_NODE, but renamed to indicate it traverses
|
||||
* through a bit map of master interfaces.
|
||||
*/
|
||||
#define FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, bit_map) \
|
||||
FOR_EACH_BIT(iface_id, bit_map)
|
||||
#endif /* __CCN_PRIVATE_H__ */
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CCN_H__
|
||||
#define __CCN_H__
|
||||
|
||||
/*
|
||||
* This macro defines the maximum number of master interfaces that reside on
|
||||
* Request nodes which the CCN driver can accommodate. The driver APIs to add
|
||||
* and remove Request nodes from snoop/dvm domains take a bit map of master
|
||||
* interfaces as inputs. The largest C data type that can be used is a 64-bit
|
||||
* unsigned integer. Hence the value of 64. The platform will have to ensure
|
||||
* that the master interfaces are numbered from 0-63.
|
||||
*/
|
||||
#define CCN_MAX_RN_MASTERS 64
|
||||
|
||||
/*
|
||||
* The following constants define the various run modes that the platform can
|
||||
* request the CCN driver to place the L3 cache in. These map to the
|
||||
* programmable P-State values in a HN-F P-state register.
|
||||
*/
|
||||
#define CCN_L3_RUN_MODE_NOL3 0x0 /* HNF_PM_NOL3 */
|
||||
#define CCN_L3_RUN_MODE_SFONLY 0x1 /* HNF_PM_SFONLY */
|
||||
#define CCN_L3_RUN_MODE_HAM 0x2 /* HNF_PM_HALF */
|
||||
#define CCN_L3_RUN_MODE_FAM 0x3 /* HNF_PM_FULL */
|
||||
|
||||
/*
|
||||
* The following macro takes the value returned from a read of a HN-F P-state
|
||||
* status register and returns the retention state value.
|
||||
*/
|
||||
#define CCN_GET_RETENTION_STATE(pstate) ((pstate >> 4) & 0x3)
|
||||
|
||||
/*
|
||||
* The following macro takes the value returned from a read of a HN-F P-state
|
||||
* status register and returns the run state value.
|
||||
*/
|
||||
#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* This structure describes some of the implementation defined attributes of the
|
||||
* CCN IP. It is used by the platform port to specify these attributes in order
|
||||
* to initialise the CCN driver. The attributes are described below.
|
||||
*
|
||||
* 1. The 'num_masters' field specifies the total number of master interfaces
|
||||
* resident on Request nodes.
|
||||
*
|
||||
* 2. The 'master_to_rn_id_map' field is a ponter to an array in which each
|
||||
* index corresponds to a master interface and its value corresponds to the
|
||||
* Request node on which the master interface resides.
|
||||
* This field is not simply defined as an array of size CCN_MAX_RN_MASTERS.
|
||||
* In reality, a platform will have much fewer master * interfaces than
|
||||
* CCN_MAX_RN_MASTERS. With an array of this size, it would also have to
|
||||
* set the unused entries to a suitable value. Zeroing the array would not
|
||||
* be enough since 0 is also a valid node id. Hence, such an array is not
|
||||
* used.
|
||||
*
|
||||
* 3. The 'periphbase' field is the base address of the programmer's view of the
|
||||
* CCN IP.
|
||||
*/
|
||||
typedef struct ccn_desc {
|
||||
unsigned int num_masters;
|
||||
const unsigned char *master_to_rn_id_map;
|
||||
uintptr_t periphbase;
|
||||
} ccn_desc_t;
|
||||
|
||||
|
||||
void ccn_init(const ccn_desc_t *plat_ccn_desc);
|
||||
void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map);
|
||||
void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map);
|
||||
void ccn_enter_dvm_domain(unsigned long long master_iface_map);
|
||||
void ccn_exit_dvm_domain(unsigned long long master_iface_map);
|
||||
void ccn_set_l3_run_mode(unsigned int mode);
|
||||
void ccn_program_sys_addrmap(unsigned int sn0_id,
|
||||
unsigned int sn1_id,
|
||||
unsigned int sn2_id,
|
||||
unsigned int top_addr_bit0,
|
||||
unsigned int top_addr_bit1,
|
||||
unsigned char three_sn_en);
|
||||
unsigned int ccn_get_l3_run_mode(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __CCN_H__ */
|
||||
|
|
@ -74,6 +74,7 @@ PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \
|
|||
plat/common/aarch64/plat_common.c
|
||||
|
||||
BL1_SOURCES += drivers/arm/cci/cci.c \
|
||||
drivers/arm/ccn/ccn.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_memmap.c \
|
||||
drivers/io/io_storage.c \
|
||||
|
|
@ -91,6 +92,7 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
|
|||
plat/common/aarch64/platform_up_stack.S
|
||||
|
||||
BL31_SOURCES += drivers/arm/cci/cci.c \
|
||||
drivers/arm/ccn/ccn.c \
|
||||
drivers/arm/gic/arm_gic.c \
|
||||
drivers/arm/gic/gic_v2.c \
|
||||
drivers/arm/gic/gic_v3.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue