PSCI: Migrate SPDs and TSP to the new platform and framework API
The new PSCI frameworks mandates that the platform APIs and the various frameworks in Trusted Firmware migrate away from MPIDR based core identification to one based on core index. Deprecated versions of the old APIs are still present to provide compatibility but their implementations are not optimal. This patch migrates the various SPDs exisiting within Trusted Firmware tree and TSP to the new APIs. Change-Id: Ifc37e7071c5769b5ded21d0b6a071c8c4cab7836
This commit is contained in:
Soby Mathew
Achin Gupta
parent
a6bd5ffbb0
commit
fd650ff61b
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -122,8 +122,7 @@ func tsp_entrypoint
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Perform early platform setup & platform
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@ -248,8 +247,7 @@ func tsp_cpu_on_entry
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* enabled.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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bl plat_set_my_stack
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/* --------------------------------------------
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* Enable the MMU with the DCache disabled. It
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@ -49,8 +49,7 @@
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******************************************************************************/
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void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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tsp_stats[linear_id].sync_fiq_count++;
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if (type == TSP_HANDLE_FIQ_AND_RETURN)
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@ -59,9 +58,9 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n",
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mpidr, elr_el3);
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read_mpidr(), elr_el3);
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VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n",
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mpidr,
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read_mpidr(),
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tsp_stats[linear_id].sync_fiq_count,
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tsp_stats[linear_id].sync_fiq_ret_count);
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spin_unlock(&console_lock);
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@ -77,8 +76,7 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
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******************************************************************************/
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int32_t tsp_fiq_handler(void)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr), id;
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uint32_t linear_id = plat_my_core_pos(), id;
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/*
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* Get the highest priority pending interrupt id and see if it is the
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@ -105,9 +103,9 @@ int32_t tsp_fiq_handler(void)
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx handled fiq %d\n",
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mpidr, id);
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read_mpidr(), id);
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VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n",
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mpidr, tsp_stats[linear_id].fiq_count);
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read_mpidr(), tsp_stats[linear_id].fiq_count);
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spin_unlock(&console_lock);
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#endif
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return 0;
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@ -115,15 +113,14 @@ int32_t tsp_fiq_handler(void)
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int32_t tsp_irq_received(void)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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tsp_stats[linear_id].irq_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx received irq\n", mpidr);
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VERBOSE("TSP: cpu 0x%lx received irq\n", read_mpidr());
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VERBOSE("TSP: cpu 0x%lx: %d irq requests\n",
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mpidr, tsp_stats[linear_id].irq_count);
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read_mpidr(), tsp_stats[linear_id].irq_count);
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spin_unlock(&console_lock);
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#endif
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return TSP_PREEMPTED;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -72,7 +72,6 @@ static tsp_args_t *set_smc_args(uint64_t arg0,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id;
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tsp_args_t *pcpu_smc_args;
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@ -80,7 +79,7 @@ static tsp_args_t *set_smc_args(uint64_t arg0,
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* Return to Secure Monitor by raising an SMC. The results of the
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* service are passed as an arguments to the SMC
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*/
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linear_id = platform_get_core_pos(mpidr);
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linear_id = plat_my_core_pos();
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pcpu_smc_args = &tsp_smc_args[linear_id];
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write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0);
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write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1);
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@ -107,8 +106,7 @@ uint64_t tsp_main(void)
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INFO("TSP: Total memory size : 0x%lx bytes\n",
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BL32_TOTAL_LIMIT - BL32_TOTAL_BASE);
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Initialize the platform */
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tsp_platform_setup();
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@ -123,7 +121,8 @@ uint64_t tsp_main(void)
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_on_count);
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@ -139,8 +138,7 @@ uint64_t tsp_main(void)
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******************************************************************************/
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tsp_args_t *tsp_cpu_on_main(void)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Initialize secure/applications state here */
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tsp_generic_timer_start();
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@ -152,8 +150,9 @@ tsp_args_t *tsp_cpu_on_main(void)
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx turned on\n", mpidr);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
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INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_on_count);
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@ -176,8 +175,7 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/*
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* This cpu is being turned off, so disable the timer to prevent the
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@ -193,8 +191,9 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx off request\n", mpidr);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", mpidr,
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INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_off_count);
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@ -219,8 +218,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/*
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* Save the time context and disable it to prevent the secure timer
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@ -237,7 +235,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
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mpidr,
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_suspend_count);
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@ -262,8 +260,7 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Restore the generic timer context */
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tsp_generic_timer_restore();
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@ -276,9 +273,9 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n",
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mpidr, suspend_level);
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read_mpidr(), suspend_level);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
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mpidr,
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_suspend_count);
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@ -301,8 +298,7 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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@ -310,8 +306,8 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", mpidr);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
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INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count);
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spin_unlock(&console_lock);
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@ -334,8 +330,7 @@ tsp_args_t *tsp_system_reset_main(uint64_t arg0,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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@ -343,8 +338,8 @@ tsp_args_t *tsp_system_reset_main(uint64_t arg0,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", mpidr);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
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INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count);
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spin_unlock(&console_lock);
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@ -371,17 +366,16 @@ tsp_args_t *tsp_smc_handler(uint64_t func,
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{
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uint64_t results[2];
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uint64_t service_args[2];
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", mpidr,
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INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", read_mpidr(),
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((func >> 31) & 1) == 1 ? "fast" : "standard",
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func);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", mpidr,
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -92,7 +92,7 @@ void tsp_generic_timer_stop(void)
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******************************************************************************/
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void tsp_generic_timer_save(void)
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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uint32_t linear_id = plat_my_core_pos();
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pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
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pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
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@ -105,7 +105,7 @@ void tsp_generic_timer_save(void)
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******************************************************************************/
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void tsp_generic_timer_restore(void)
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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uint32_t linear_id = plat_my_core_pos();
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write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
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write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -80,7 +80,6 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
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void *cookie)
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{
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uint32_t linear_id;
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uint64_t mpidr;
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optee_context_t *optee_ctx;
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/* Check the security state when the exception was generated */
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@ -92,14 +91,13 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
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#endif
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/* Sanity check the pointer to this cpu's context */
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mpidr = read_mpidr();
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assert(handle == cm_get_context(NON_SECURE));
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/* Save the non-secure context before entering the OPTEE */
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cm_el1_sysregs_context_save(NON_SECURE);
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/* Get a reference to this cpu's OPTEE context */
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linear_id = platform_get_core_pos(mpidr);
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linear_id = plat_my_core_pos();
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optee_ctx = &opteed_sp_context[linear_id];
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assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE));
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@ -125,10 +123,9 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
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int32_t opteed_setup(void)
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{
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entry_point_info_t *optee_ep_info;
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id;
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linear_id = platform_get_core_pos(mpidr);
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linear_id = plat_my_core_pos();
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/*
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* Get information about the Secure Payload (BL32) image. Its
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@ -182,8 +179,7 @@ int32_t opteed_setup(void)
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******************************************************************************/
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static int32_t opteed_init(void)
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{
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uint64_t mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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uint32_t linear_id = plat_my_core_pos();
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optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
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entry_point_info_t *optee_entry_point;
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uint64_t rc;
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|
|
@ -195,7 +191,7 @@ static int32_t opteed_init(void)
|
|||
optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
assert(optee_entry_point);
|
||||
|
||||
cm_init_context(mpidr, optee_entry_point);
|
||||
cm_init_my_context(optee_entry_point);
|
||||
|
||||
/*
|
||||
* Arrange for an entry into OPTEE. It will be returned via
|
||||
|
|
@ -226,8 +222,7 @@ uint64_t opteed_smc_handler(uint32_t smc_fid,
|
|||
uint64_t flags)
|
||||
{
|
||||
cpu_context_t *ns_cpu_context;
|
||||
unsigned long mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
uint64_t rc;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -51,8 +51,7 @@ static void opteed_cpu_on_handler(uint64_t target_cpu)
|
|||
static int32_t opteed_cpu_off_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
|
||||
assert(optee_vectors);
|
||||
|
|
@ -85,8 +84,7 @@ static int32_t opteed_cpu_off_handler(uint64_t unused)
|
|||
static void opteed_cpu_suspend_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
|
||||
assert(optee_vectors);
|
||||
|
|
@ -116,8 +114,7 @@ static void opteed_cpu_suspend_handler(uint64_t unused)
|
|||
static void opteed_cpu_on_finish_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
entry_point_info_t optee_on_entrypoint;
|
||||
|
||||
|
|
@ -129,7 +126,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
|
|||
optee_ctx);
|
||||
|
||||
/* Initialise this cpu's secure context */
|
||||
cm_init_context(mpidr, &optee_on_entrypoint);
|
||||
cm_init_my_context(&optee_on_entrypoint);
|
||||
|
||||
/* Enter OPTEE */
|
||||
rc = opteed_synchronous_sp_entry(optee_ctx);
|
||||
|
|
@ -153,8 +150,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
|
|||
static void opteed_cpu_suspend_finish_handler(uint64_t suspend_level)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
|
||||
assert(optee_vectors);
|
||||
|
|
@ -193,8 +189,7 @@ static int32_t opteed_cpu_migrate_info(uint64_t *resident_cpu)
|
|||
******************************************************************************/
|
||||
static void opteed_system_off(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
|
||||
assert(optee_vectors);
|
||||
|
|
@ -214,8 +209,7 @@ static void opteed_system_off(void)
|
|||
******************************************************************************/
|
||||
static void opteed_system_reset(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
|
||||
|
||||
assert(optee_vectors);
|
||||
|
|
|
|||
|
|
@ -121,7 +121,6 @@ int32_t tlkd_setup(void)
|
|||
******************************************************************************/
|
||||
int32_t tlkd_init(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
entry_point_info_t *tlk_entry_point;
|
||||
|
||||
/*
|
||||
|
|
@ -131,7 +130,7 @@ int32_t tlkd_init(void)
|
|||
tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
assert(tlk_entry_point);
|
||||
|
||||
cm_init_context(mpidr, tlk_entry_point);
|
||||
cm_init_my_context(tlk_entry_point);
|
||||
|
||||
/*
|
||||
* Arrange for an entry into the test secure payload.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -101,7 +101,6 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
|
|||
void *cookie)
|
||||
{
|
||||
uint32_t linear_id;
|
||||
uint64_t mpidr;
|
||||
tsp_context_t *tsp_ctx;
|
||||
|
||||
/* Check the security state when the exception was generated */
|
||||
|
|
@ -113,14 +112,13 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
|
|||
#endif
|
||||
|
||||
/* Sanity check the pointer to this cpu's context */
|
||||
mpidr = read_mpidr();
|
||||
assert(handle == cm_get_context(NON_SECURE));
|
||||
|
||||
/* Save the non-secure context before entering the TSP */
|
||||
cm_el1_sysregs_context_save(NON_SECURE);
|
||||
|
||||
/* Get a reference to this cpu's TSP context */
|
||||
linear_id = platform_get_core_pos(mpidr);
|
||||
linear_id = plat_my_core_pos();
|
||||
tsp_ctx = &tspd_sp_context[linear_id];
|
||||
assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
|
||||
|
||||
|
|
@ -197,10 +195,9 @@ static uint64_t tspd_ns_interrupt_handler(uint32_t id,
|
|||
int32_t tspd_setup(void)
|
||||
{
|
||||
entry_point_info_t *tsp_ep_info;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id;
|
||||
|
||||
linear_id = platform_get_core_pos(mpidr);
|
||||
linear_id = plat_my_core_pos();
|
||||
|
||||
/*
|
||||
* Get information about the Secure Payload (BL32) image. Its
|
||||
|
|
@ -256,8 +253,7 @@ int32_t tspd_setup(void)
|
|||
******************************************************************************/
|
||||
int32_t tspd_init(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
entry_point_info_t *tsp_entry_point;
|
||||
uint64_t rc;
|
||||
|
|
@ -269,7 +265,7 @@ int32_t tspd_init(void)
|
|||
tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
assert(tsp_entry_point);
|
||||
|
||||
cm_init_context(mpidr, tsp_entry_point);
|
||||
cm_init_my_context(tsp_entry_point);
|
||||
|
||||
/*
|
||||
* Arrange for an entry into the test secure payload. It will be
|
||||
|
|
@ -300,8 +296,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
uint64_t flags)
|
||||
{
|
||||
cpu_context_t *ns_cpu_context;
|
||||
unsigned long mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr), ns;
|
||||
uint32_t linear_id = plat_my_core_pos(), ns;
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
uint64_t rc;
|
||||
#if TSP_INIT_ASYNC
|
||||
|
|
@ -453,7 +448,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
|
||||
/*
|
||||
* Disable the interrupt NS locally since it will be enabled globally
|
||||
* within cm_init_context.
|
||||
* within cm_init_my_context.
|
||||
*/
|
||||
disable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
|
|
@ -471,7 +466,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
assert(NON_SECURE ==
|
||||
GET_SECURITY_STATE(next_image_info->h.attr));
|
||||
|
||||
cm_init_context(read_mpidr_el1(), next_image_info);
|
||||
cm_init_my_context(next_image_info);
|
||||
cm_prepare_el3_exit(NON_SECURE);
|
||||
SMC_RET0(cm_get_context(NON_SECURE));
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -52,8 +52,7 @@ static void tspd_cpu_on_handler(uint64_t target_cpu)
|
|||
static int32_t tspd_cpu_off_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
|
||||
assert(tsp_vectors);
|
||||
|
|
@ -86,8 +85,7 @@ static int32_t tspd_cpu_off_handler(uint64_t unused)
|
|||
static void tspd_cpu_suspend_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
|
||||
assert(tsp_vectors);
|
||||
|
|
@ -117,8 +115,7 @@ static void tspd_cpu_suspend_handler(uint64_t unused)
|
|||
static void tspd_cpu_on_finish_handler(uint64_t unused)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
entry_point_info_t tsp_on_entrypoint;
|
||||
|
||||
|
|
@ -131,12 +128,12 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
|
|||
tsp_ctx);
|
||||
|
||||
/* Initialise this cpu's secure context */
|
||||
cm_init_context(mpidr, &tsp_on_entrypoint);
|
||||
cm_init_my_context(&tsp_on_entrypoint);
|
||||
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
/*
|
||||
* Disable the NS interrupt locally since it will be enabled globally
|
||||
* within cm_init_context.
|
||||
* within cm_init_my_context.
|
||||
*/
|
||||
disable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
|
|
@ -163,8 +160,7 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
|
|||
static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
|
||||
assert(tsp_vectors);
|
||||
|
|
@ -203,8 +199,7 @@ static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu)
|
|||
******************************************************************************/
|
||||
static void tspd_system_off(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
|
||||
assert(tsp_vectors);
|
||||
|
|
@ -224,8 +219,7 @@ static void tspd_system_off(void)
|
|||
******************************************************************************/
|
||||
static void tspd_system_reset(void)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
uint32_t linear_id = platform_get_core_pos(mpidr);
|
||||
uint32_t linear_id = plat_my_core_pos();
|
||||
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
|
||||
|
||||
assert(tsp_vectors);
|
||||
|
|
|
|||
Loading…
Reference in New Issue