Merge changes from topic "revert-14286-uart_segregation-VURJFOWMTM" into integration
* changes: Revert "feat(sgi): deviate from arm css common uart related defi..." Revert "feat(sgi): route TF-A logs via secure uart" Revert "feat(sgi): add page table translation entry for secure uart"
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
fdbbd59e97
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -35,8 +35,8 @@
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# if SPM_MM
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# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define PLAT_SP_IMAGE_MMAP_REGIONS 10
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12
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# define PLAT_SP_IMAGE_MMAP_REGIONS 9
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11
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# else
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# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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@ -130,21 +130,6 @@
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/* PL011 UART related constants */
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#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
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#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
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#define SOC_CSS_UART_SIZE UL(0x10000)
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#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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@ -273,18 +258,4 @@
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
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#if SPM_MM
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/*
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* Stand-alone MM logs would be routed via secure UART. Define page table
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* entry for secure UART which would be common to all platforms.
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*/
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#define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \
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SOC_CSS_SEC_UART_BASE, \
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SOC_CSS_UART_SIZE, \
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MT_DEVICE | MT_RW | \
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MT_SECURE | MT_USER)
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#endif
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#endif /* SGI_BASE_PLATFORM_DEF_H */
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@ -1,47 +0,0 @@
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/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SGI_SOC_CSS_DEF_H
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#define SGI_SOC_CSS_DEF_H
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#include <lib/utils_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <plat/common/common_def.h>
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/*
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* Definitions common to all ARM CSSv1-based development platforms
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*/
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/* Platform ID address */
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#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x7ffe00e0)
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/* Platform ID related accessors */
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#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
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#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
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#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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#define BOARD_CSS_GET_PLAT_TYPE(addr) \
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((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
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>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
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#endif /* __ASSEMBLER__ */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#endif /* SGI_SOC_CSS_DEF_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -24,10 +24,17 @@
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#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
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/* PL011 UART related constants */
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#define SOC_CSS_UART1_BASE UL(0x0ef80000)
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#define SOC_CSS_UART0_BASE UL(0x0ef70000)
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/* Memory controller */
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#define SOC_MEMCNTRL_BASE UL(0x10000000)
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#define SOC_MEMCNTRL_SIZE UL(0x10000000)
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#define SOC_CSS_UART0_CLK_IN_HZ UL(7372800)
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#define SOC_CSS_UART1_CLK_IN_HZ UL(7372800)
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
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@ -199,4 +206,17 @@
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#endif /* SGI_SOC_CSS_DEF_V2_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,10 +7,10 @@
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#ifndef SGI_SOC_PLATFORM_DEF_H
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#define SGI_SOC_PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <plat/arm/board/common/board_css_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <sgi_base_platform_def.h>
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#include <sgi_soc_css_def.h>
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/* Map the System registers to access from S-EL0 */
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#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -89,7 +89,6 @@ const mmap_region_t plat_arm_mmap[] = {
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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PLAT_ARM_SECURE_MAP_SYSTEMREG,
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PLAT_ARM_SECURE_MAP_NOR2,
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SOC_PLATFORM_SECURE_UART,
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PLAT_ARM_SECURE_MAP_DEVICE,
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -83,7 +83,6 @@ const mmap_region_t plat_arm_mmap[] = {
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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PLAT_ARM_SECURE_MAP_SYSTEMREG,
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PLAT_ARM_SECURE_MAP_NOR2,
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SOC_PLATFORM_SECURE_UART,
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SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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