Tegra210: SiP handlers to allow PMC access
This patch adds SiP handler for Tegra210 platforms to service read/write requests for PMC block. None of the secure registers are accessible to the NS world though. Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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@ -14,18 +14,29 @@
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#include <tegra_def.h>
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#include <tegra_def.h>
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#define PMC_CONFIG U(0x0)
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#define PMC_CONFIG U(0x0)
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#define PMC_DPD_ENABLE_0 U(0x24)
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#define PMC_PWRGATE_STATUS U(0x38)
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#define PMC_PWRGATE_STATUS U(0x38)
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#define PMC_PWRGATE_TOGGLE U(0x30)
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#define PMC_PWRGATE_TOGGLE U(0x30)
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#define PMC_SECURE_SCRATCH0 U(0xb0)
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#define PMC_SECURE_SCRATCH5 U(0xc4)
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#define PMC_CRYPTO_OP_0 U(0xf4)
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#define PMC_TOGGLE_START U(0x100)
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#define PMC_TOGGLE_START U(0x100)
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#define PMC_SCRATCH39 U(0x138)
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#define PMC_SCRATCH39 U(0x138)
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#define PMC_SECURE_SCRATCH6 U(0x224)
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#define PMC_SECURE_SCRATCH7 U(0x228)
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#define PMC_SECURE_DISABLE2 U(0x2c4)
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#define PMC_SECURE_DISABLE2 U(0x2c4)
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#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28)
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#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28)
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#define PMC_SECURE_SCRATCH8 U(0x300)
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#define PMC_SECURE_SCRATCH79 U(0x41c)
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#define PMC_FUSE_CONTROL_0 U(0x450)
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#define PMC_SECURE_SCRATCH22 U(0x338)
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#define PMC_SECURE_SCRATCH22 U(0x338)
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#define PMC_SECURE_DISABLE3 U(0x2d8)
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#define PMC_SECURE_DISABLE3 U(0x2d8)
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#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20)
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#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20)
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#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22)
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#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22)
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#define PMC_SECURE_SCRATCH34 U(0x368)
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#define PMC_SECURE_SCRATCH34 U(0x368)
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#define PMC_SECURE_SCRATCH35 U(0x36c)
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#define PMC_SECURE_SCRATCH35 U(0x36c)
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#define PMC_SECURE_SCRATCH80 U(0xa98)
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#define PMC_SECURE_SCRATCH119 U(0xb34)
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#define PMC_SCRATCH201 U(0x844)
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#define PMC_SCRATCH201 U(0x844)
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static inline uint32_t tegra_pmc_read_32(uint32_t off)
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static inline uint32_t tegra_pmc_read_32(uint32_t off)
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@ -196,6 +196,7 @@
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* Tegra Power Mgmt Controller constants
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x7000E400)
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#define TEGRA_PMC_BASE U(0x7000E400)
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#define TEGRA_PMC_SIZE U(0xC00) /* 3k */
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Atomics constants
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* Tegra Atomics constants
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@ -0,0 +1,90 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <errno.h>
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#include <mmio.h>
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#include <utils_def.h>
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#include <memctrl.h>
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#include <pmc.h>
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#include <tegra_private.h>
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#include <tegra_platform.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* PMC parameters
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******************************************************************************/
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#define PMC_READ U(0xaa)
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#define PMC_WRITE U(0xbb)
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/*******************************************************************************
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* Tegra210 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00)
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/*******************************************************************************
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* This function is responsible for handling all T210 SiP calls
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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const void *cookie,
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void *handle,
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uint64_t flags)
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{
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uint32_t val, ns;
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/* Determine which security state this SMC originated from */
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ns = is_caller_non_secure(flags);
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if (!ns)
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SMC_RET1(handle, SMC_UNK);
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switch (smc_fid) {
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case TEGRA_SIP_PMC_COMMANDS:
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/* check the address is within PMC range and is 4byte aligned */
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if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3))
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return -EINVAL;
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/* pmc_secure_scratch registers are not accessible */
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if (((x2 >= PMC_SECURE_SCRATCH0) && (x2 <= PMC_SECURE_SCRATCH5)) ||
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((x2 >= PMC_SECURE_SCRATCH6) && (x2 <= PMC_SECURE_SCRATCH7)) ||
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((x2 >= PMC_SECURE_SCRATCH8) && (x2 <= PMC_SECURE_SCRATCH79)) ||
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((x2 >= PMC_SECURE_SCRATCH80) && (x2 <= PMC_SECURE_SCRATCH119)))
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return -EFAULT;
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/* PMC secure-only registers are not accessible */
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if ((x2 == PMC_DPD_ENABLE_0) || (x2 == PMC_FUSE_CONTROL_0) ||
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(x2 == PMC_CRYPTO_OP_0))
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return -EFAULT;
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/* Perform PMC read/write */
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if (x1 == PMC_READ) {
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val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2));
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val);
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} else if (x1 == PMC_WRITE) {
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mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3);
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} else {
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return -EINVAL;
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}
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break;
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default:
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ERROR("%s: unsupported function ID\n", __func__);
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return -ENOTSUP;
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}
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return 0;
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}
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@ -36,7 +36,8 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/drivers/se/security_engine.c \
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${SOC_DIR}/drivers/se/security_engine.c \
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${SOC_DIR}/plat_secondary.c
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${SOC_DIR}/plat_secondary.c \
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${SOC_DIR}/plat_sip_calls.c
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# Enable workarounds for selected Cortex-A57 erratas.
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# Enable workarounds for selected Cortex-A57 erratas.
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A57_DISABLE_NON_TEMPORAL_HINT := 1
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A57_DISABLE_NON_TEMPORAL_HINT := 1
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