tegra: Migrate to new interfaces
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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@ -23,13 +23,13 @@
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#include <utils.h>
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#include <utils_def.h>
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/* length of Trusty's input parameters (in bytes) */
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#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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extern void zeromem16(void *mem, unsigned int length);
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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@ -72,7 +72,7 @@ void plat_early_platform_setup(void)
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; /* do nothing */
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}
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bl31_params_t *plat_get_bl31_params(void)
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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return NULL;
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}
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@ -112,11 +112,11 @@ plat_params_from_bl2_t *bl31_get_plat_params(void)
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* Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
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* info.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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plat_params_from_bl2_t *plat_params =
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(plat_params_from_bl2_t *)plat_params_from_bl2;
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struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
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plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
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image_info_t bl32_img_info = { {0} };
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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@ -126,8 +126,8 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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* might use custom ways to get arguments, so provide handlers which
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* they can override.
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*/
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if (from_bl2 == NULL)
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from_bl2 = plat_get_bl31_params();
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if (arg_from_bl2 == NULL)
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arg_from_bl2 = plat_get_bl31_params();
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if (plat_params == NULL)
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plat_params = plat_get_bl31_plat_params();
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@ -135,14 +135,14 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(from_bl2);
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assert(from_bl2->bl33_ep_info);
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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assert(arg_from_bl2);
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assert(arg_from_bl2->bl33_ep_info);
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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if (from_bl2->bl32_ep_info) {
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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bl32_mem_size = from_bl2->bl32_ep_info->args.arg0;
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bl32_boot_params = from_bl2->bl32_ep_info->args.arg2;
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if (arg_from_bl2->bl32_ep_info) {
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
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bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
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}
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/*
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@ -191,9 +191,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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* inside the TZDRAM. We check the BL32 image info to find out
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* the base/PC values and relocate the image if necessary.
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*/
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if (from_bl2->bl32_image_info) {
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if (arg_from_bl2->bl32_image_info) {
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bl32_img_info = *from_bl2->bl32_image_info;
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bl32_img_info = *arg_from_bl2->bl32_image_info;
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/* Relocate BL32 if it resides outside of the TZDRAM */
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tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
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@ -217,7 +217,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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bl32_img_info.image_size);
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/* clean up non-secure intermediate buffer */
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zeromem16((void *)(uintptr_t)bl32_start,
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zeromem((void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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}
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}
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -13,8 +13,7 @@ PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
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COMMON_DIR := plat/nvidia/tegra/common
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BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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drivers/console/aarch64/console.S \
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BL31_SOURCES += drivers/console/aarch64/console.S \
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drivers/delay_timer/delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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${COMMON_DIR}/aarch64/tegra_helpers.S \
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@ -12,7 +12,6 @@
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#include <context_mgmt.h>
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#include <debug.h>
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#include <denver.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <tegra_def.h>
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@ -5,11 +5,9 @@
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*/
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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@ -188,14 +186,9 @@ static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
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* both normal and secure worlds are using ARM GICv2. This parameter
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* will be used when the secure world starts using GICv3.
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*/
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#if ARM_GIC_ARCH == 2
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return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type);
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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}
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#if ARM_GIC_ARCH == 2
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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return ret;
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}
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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return tegra_gic_get_pending_interrupt_id();
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@ -7,7 +7,6 @@
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#ifndef __PLAT_MACROS_S__
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#define __PLAT_MACROS_S__
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#include <gic_v2.h>
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#include <tegra_def.h>
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.section .rodata.gic_reg_name, "aS"
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@ -50,6 +50,18 @@ typedef struct irq_sec_cfg {
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uint32_t type;
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} irq_sec_cfg_t;
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/*******************************************************************************
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* Struct describing parameters passed to bl31
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******************************************************************************/
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struct tegra_bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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/* Declarations for plat_psci_handlers.c */
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state);
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const mmap_region_t *plat_get_mmio_map(void);
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uint32_t plat_get_console_from_id(int id);
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void plat_gic_setup(void);
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bl31_params_t *plat_get_bl31_params(void);
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struct tegra_bl31_params *plat_get_bl31_params(void);
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
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/* Declarations for plat_secondary.c */
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@ -13,9 +13,6 @@ $(eval $(call add_define,CRASH_REPORTING))
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# enable assert() for release/debug builds
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ENABLE_ASSERTIONS := 1
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# Disable the PSCI platform compatibility layer
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ENABLE_PLAT_COMPAT := 0
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# enable dynamic memory mapping
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PLAT_XLAT_TABLES_DYNAMIC := 1
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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@ -217,13 +217,13 @@ void plat_gic_setup(void)
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/*******************************************************************************
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* Return pointer to the BL31 params from previous bootloader
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******************************************************************************/
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bl31_params_t *plat_get_bl31_params(void)
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
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return (bl31_params_t *)(uintptr_t)val;
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return (struct tegra_bl31_params *)(uintptr_t)val;
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}
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/*******************************************************************************
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