Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration

This commit is contained in:
Manish Pandey 2021-01-06 18:24:22 +00:00 committed by TrustedFirmware Code Review
commit fde125cb61
6 changed files with 102 additions and 5 deletions

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@ -86,6 +86,20 @@ There are several build options:
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
- CM3_SYSTEM_RESET
For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will
be used for system reset.
TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
Cortex-M3 secure coprocessor.
The firmware running in the coprocessor must either implement this functionality or
ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell
repository). If this option is enabled but the firmware does not support this command,
an error message will be printed prior trying to reboot via the usual way.
This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
sometime hang the board.
- MARVELL_SECURE_BOOT
Build trusted(=1)/non trusted(=0) image, default is non trusted.
@ -209,7 +223,8 @@ To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run f
.. code:: shell
> make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
> make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \
CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
Supported MARVELL_PLATFORM are:
- a3700 (for both A3720 DB and EspressoBin)

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@ -1,5 +1,5 @@
#
# Copyright (C) 2018 Marvell International Ltd.
# Copyright (C) 2018-2020 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
@ -64,6 +64,10 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
$(PLAT_COMMON_BASE)/a3700_sip_svc.c \
$(MARVELL_DRV)
ifeq ($(CM3_SYSTEM_RESET),1)
BL31_SOURCES += $(PLAT_COMMON_BASE)/cm3_system_reset.c
endif
ifdef WTP
DOIMAGEPATH := $(WTP)

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@ -0,0 +1,62 @@
/*
* Copyright (C) 2020 Marek Behun, CZ.NIC
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <stdbool.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <mvebu_def.h>
/* Cortex-M3 Secure Processor Mailbox Registers */
#define MVEBU_RWTM_PARAM0_REG (MVEBU_RWTM_REG_BASE)
#define MVEBU_RWTM_CMD_REG (MVEBU_RWTM_REG_BASE + 0x40)
#define MVEBU_RWTM_HOST_INT_RESET_REG (MVEBU_RWTM_REG_BASE + 0xC8)
#define MVEBU_RWTM_HOST_INT_MASK_REG (MVEBU_RWTM_REG_BASE + 0xCC)
#define MVEBU_RWTM_HOST_INT_SP_COMPLETE BIT(0)
#define MVEBU_RWTM_REBOOT_CMD 0x0009
#define MVEBU_RWTM_REBOOT_MAGIC 0xDEADBEEF
static inline bool rwtm_completed(void)
{
return (mmio_read_32(MVEBU_RWTM_HOST_INT_RESET_REG) &
MVEBU_RWTM_HOST_INT_SP_COMPLETE) != 0;
}
static bool rwtm_wait(int ms)
{
while (ms && !rwtm_completed()) {
mdelay(1);
--ms;
}
return rwtm_completed();
}
void cm3_system_reset(void)
{
int tries = 5;
for (; tries > 0; --tries) {
mmio_clrbits_32(MVEBU_RWTM_HOST_INT_RESET_REG,
MVEBU_RWTM_HOST_INT_SP_COMPLETE);
mmio_write_32(MVEBU_RWTM_PARAM0_REG, MVEBU_RWTM_REBOOT_MAGIC);
mmio_write_32(MVEBU_RWTM_CMD_REG, MVEBU_RWTM_REBOOT_CMD);
if (rwtm_wait(10)) {
break;
}
mdelay(100);
}
/* If we reach here, the command is not implemented. */
ERROR("System reset command not implemented in WTMI firmware!\n");
}

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@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
* Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@ -119,4 +119,10 @@
*/
#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
/*****************************************************************************
* Cortex-M3 Secure Processor Mailbox constants
*****************************************************************************
*/
#define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000)
#endif /* A3700_PLAT_DEF_H */

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@ -1,5 +1,5 @@
/*
* Copyright (C) 2016 Marvell International Ltd.
* Copyright (C) 2016-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@ -48,4 +48,6 @@ struct pm_wake_up_src_config {
struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
void cm3_system_reset(void);
#endif /* A3700_PM_H */

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@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
* Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@ -763,6 +763,11 @@ static void __dead2 a3700_system_off(void)
panic();
}
#pragma weak cm3_system_reset
void cm3_system_reset(void)
{
}
/*****************************************************************************
* A3700 handlers to reset the system
*****************************************************************************
@ -780,6 +785,9 @@ static void __dead2 a3700_system_reset(void)
2 * sizeof(uint64_t));
#endif
/* Use Cortex-M3 secure coprocessor for system reset */
cm3_system_reset();
/* Trigger the warm reset */
mmio_write_32(MVEBU_WARM_RESET_REG, MVEBU_WARM_RESET_MAGIC);