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plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay 

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989
This commit is contained in:
Sai Krishna Potthuri 2020-10-30 00:09:43 -06:00 committed by Michal Simek
parent 2ab0ef8db9
commit fe1fa205fc
1 changed files with 10 additions and 5 deletions
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15
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View File

@ -312,9 +312,15 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
(ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK << shift),
(ZYNQMP_SD_ITAPDLYENA << shift));
if (value == 0)
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), 0);
else
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), (ZYNQMP_SD_ITAPDLYENA <<
shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
@ -326,8 +332,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYENA_MASK << shift),
(ZYNQMP_SD_OTAPDLYENA << shift));
(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,