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drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC 

Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
This commit is contained in:
Lad Prabhakar 2021-04-19 16:59:55 +01:00
parent 778db0e924
commit fe5929c19d
3 changed files with 95 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
View File

@ -37,6 +37,7 @@
#define RCAR_H3N 4
#define RZ_G2M 100U
#define RZ_G2H 101U
#define RCAR_CUT_10 0
#define RCAR_CUT_11 1
@ -57,7 +58,7 @@ static const uint32_t prr_product = PRR_PRODUCT_H3;
static const uint32_t prr_product = PRR_PRODUCT_M3;
#elif(RCAR_LSI == RCAR_M3N)
static const uint32_t prr_product = PRR_PRODUCT_M3N;
#elif(RCAR_LSI == RCAR_H3N)
#elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H)
static const uint32_t prr_product = PRR_PRODUCT_H3;
#endif /* RCAR_LSI */

92
drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
View File

@ -10,7 +10,7 @@
#endif
#if (RZG_SOC == 1)
#define BOARDNUM 2
#define BOARDNUM 3
#else
#define BOARDNUM 22
#endif /* RZG_SOC == 1 */
@ -173,6 +173,93 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
},
/* boardcnf[2] HopeRun HiHope RZ/G2H board 16Gbit/1rank/2ch */
{
0x05U,
0x01U,
0x0300U,
0,
0x0300U,
0x00a0U,
{
{
{ 0x04U, 0xffU },
0x00345201UL,
0x3201U,
{ 0x01672543U, 0x45367012U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x04U, 0xffU },
0x00302154UL,
0x2310U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x04U, 0xffU },
0x00302154UL,
0x2310U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0xffU, 0xffU },
0UL,
0U,
{ 0U, 0U, 0U, 0U },
{ 0U, 0U, 0U, 0U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
}
};
#else
@ -1836,6 +1923,9 @@ static uint32_t rzg2_board_judge(void)
}
}
break;
case PRR_PRODUCT_H3:
brd = 2U;
break;
default:
brd = 99U;
}

2
plat/renesas/common/common.mk
View File

@ -34,6 +34,7 @@ RCAR_D3:=5
RCAR_V3M:=6
RCAR_AUTO:=99
RZ_G2M:=100
RZ_G2H:=101
$(eval $(call add_define,RCAR_H3))
$(eval $(call add_define,RCAR_M3))
$(eval $(call add_define,RCAR_M3N))
@ -43,6 +44,7 @@ $(eval $(call add_define,RCAR_D3))
$(eval $(call add_define,RCAR_V3M))
$(eval $(call add_define,RCAR_AUTO))
$(eval $(call add_define,RZ_G2M))
$(eval $(call add_define,RZ_G2H))
RCAR_CUT_10:=0
RCAR_CUT_11:=1