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Merge changes from topic "st_dt_update" into integration 

* changes:
  fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
  fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
  feat(fdts stm32mp1): delete nodes for non-used boot devices
  fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
  refactor(fdts stm32mp1): move STM32MP DDR node
  feat(fdts stm32mp1): align DT with latest kernel
This commit is contained in:
Manish Pandey 2021-10-29 18:11:23 +02:00 committed by TrustedFirmware Code Review
parent e33ca7b44a cdbbb9f7ec
commit fea7f36938
15 changed files with 303 additions and 201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
fdts/stm32mp15-bl2.dtsi
View File

@ -4,6 +4,12 @@
*/
/ {
#if !STM32MP_EMMC && !STM32MP_SDMMC
aliases {
/delete-property/ mmc0;
};
#endif
cpus {
/delete-node/ cpu@1;
};
@ -13,9 +19,25 @@
soc {
/delete-node/ timer@40006000;
/delete-node/ timer@44006000;
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usb-otg@49000000;
#endif
/delete-node/ pwr_mcu@50001014;
/delete-node/ cryp@54001000;
/delete-node/ rng@54003000;
#if !STM32MP_RAW_NAND
/delete-node/ memory-controller@58002000;
#endif
#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR
/delete-node/ spi@58003000;
#endif
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-node/ mmc@58005000;
/delete-node/ mmc@58007000;
#endif
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usbphyc@5a006000;
#endif
/delete-node/ spi@5c001000;
/delete-node/ rtc@5c004000;
/delete-node/ etzpc@5c007000;
@ -24,7 +46,25 @@
/delete-node/ tamp@5c00a000;
pin-controller@50002000 {
/delete-node/ rtc-out2-rmp-pins-0;
#if !STM32MP_RAW_NAND
/delete-node/ fmc-0;
#endif
#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR
/delete-node/ qspi-clk-0;
/delete-node/ qspi-bk1-0;
/delete-node/ qspi-bk2-0;
#endif
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-node/ sdmmc1-b4-0;
/delete-node/ sdmmc1-dir-0;
/delete-node/ sdmmc2-b4-0;
/delete-node/ sdmmc2-b4-1;
/delete-node/ sdmmc2-d47-0;
#endif
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usbotg_hs-0;
/delete-node/ usbotg-fs-dp-dm-0;
#endif
};
};

6
fdts/stm32mp15-bl32.dtsi
View File

@ -20,8 +20,8 @@
/delete-node/ hash@54002000;
/delete-node/ memory-controller@58002000;
/delete-node/ spi@58003000;
/delete-node/ sdmmc@58005000;
/delete-node/ sdmmc@58007000;
/delete-node/ mmc@58005000;
/delete-node/ mmc@58007000;
/delete-node/ usbphyc@5a006000;
/delete-node/ spi@5c001000;
/delete-node/ stgen@5c008000;
@ -37,6 +37,8 @@
/delete-node/ sdmmc2-b4-0;
/delete-node/ sdmmc2-b4-1;
/delete-node/ sdmmc2-d47-0;
/delete-node/ sdmmc2-d47-1;
/delete-node/ sdmmc2-d47-3;
/delete-node/ usbotg_hs-0;
/delete-node/ usbotg-fs-dp-dm-0;
};

256
fdts/stm32mp15-ddr.dtsi
View File

@ -1,153 +1,127 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*/
/ {
soc {
ddr: ddr@5a003000{
&ddr {
st,mem-name = DDR_MEM_NAME;
st,mem-speed = <DDR_MEM_SPEED>;
st,mem-size = <DDR_MEM_SIZE>;
compatible = "st,stm32mp1-ddr";
st,ctl-reg = <
DDR_MSTR
DDR_MRCTRL0
DDR_MRCTRL1
DDR_DERATEEN
DDR_DERATEINT
DDR_PWRCTL
DDR_PWRTMG
DDR_HWLPCTL
DDR_RFSHCTL0
DDR_RFSHCTL3
DDR_CRCPARCTL0
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
reg = <0x5A003000 0x550
0x5A004000 0x234>;
st,ctl-timing = <
DDR_RFSHTMG
DDR_DRAMTMG0
DDR_DRAMTMG1
DDR_DRAMTMG2
DDR_DRAMTMG3
DDR_DRAMTMG4
DDR_DRAMTMG5
DDR_DRAMTMG6
DDR_DRAMTMG7
DDR_DRAMTMG8
DDR_DRAMTMG14
DDR_ODTCFG
>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
st,ctl-map = <
DDR_ADDRMAP1
DDR_ADDRMAP2
DDR_ADDRMAP3
DDR_ADDRMAP4
DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
st,ctl-perf = <
DDR_SCHED
DDR_SCHED1
DDR_PERFHPR1
DDR_PERFLPR1
DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
DDR_PCFGR_1
DDR_PCFGW_1
DDR_PCFGQOS0_1
DDR_PCFGQOS1_1
DDR_PCFGWQOS0_1
DDR_PCFGWQOS1_1
>;
st,mem-name = DDR_MEM_NAME;
st,mem-speed = <DDR_MEM_SPEED>;
st,mem-size = <DDR_MEM_SIZE>;
st,phy-reg = <
DDR_PGCR
DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
DDR_DX2GCR
DDR_DX3GCR
>;
st,ctl-reg = <
DDR_MSTR
DDR_MRCTRL0
DDR_MRCTRL1
DDR_DERATEEN
DDR_DERATEINT
DDR_PWRCTL
DDR_PWRTMG
DDR_HWLPCTL
DDR_RFSHCTL0
DDR_RFSHCTL3
DDR_CRCPARCTL0
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
st,phy-timing = <
DDR_PTR0
DDR_PTR1
DDR_PTR2
DDR_DTPR0
DDR_DTPR1
DDR_DTPR2
DDR_MR0
DDR_MR1
DDR_MR2
DDR_MR3
>;
st,ctl-timing = <
DDR_RFSHTMG
DDR_DRAMTMG0
DDR_DRAMTMG1
DDR_DRAMTMG2
DDR_DRAMTMG3
DDR_DRAMTMG4
DDR_DRAMTMG5
DDR_DRAMTMG6
DDR_DRAMTMG7
DDR_DRAMTMG8
DDR_DRAMTMG14
DDR_ODTCFG
>;
st,ctl-map = <
DDR_ADDRMAP1
DDR_ADDRMAP2
DDR_ADDRMAP3
DDR_ADDRMAP4
DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
st,ctl-perf = <
DDR_SCHED
DDR_SCHED1
DDR_PERFHPR1
DDR_PERFLPR1
DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
DDR_PCFGR_1
DDR_PCFGW_1
DDR_PCFGQOS0_1
DDR_PCFGQOS1_1
DDR_PCFGWQOS0_1
DDR_PCFGWQOS1_1
>;
st,phy-reg = <
DDR_PGCR
DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
DDR_DX2GCR
DDR_DX3GCR
>;
st,phy-timing = <
DDR_PTR0
DDR_PTR1
DDR_PTR2
DDR_DTPR0
DDR_DTPR1
DDR_DTPR2
DDR_MR0
DDR_MR1
DDR_MR2
DDR_MR3
>;
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
status = "okay";
};
};
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
};

2
fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
View File

@ -15,7 +15,7 @@
* Save Date: 2020.02.20, save Time: 18:45:20
*/
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000

2
fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
View File

@ -15,7 +15,7 @@
* Save Date: 2020.02.20, save Time: 18:49:33
*/
#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000

109
fdts/stm32mp15-pinctrl.dtsi
View File

@ -86,12 +86,6 @@
};
};
rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@ -176,6 +170,18 @@
};
};
sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@ -213,33 +219,89 @@
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
<STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
<STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
<STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
<STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
bias-disable;
};
};
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
bias-disable;
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
<STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
<STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
@ -256,20 +318,33 @@
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
@ -284,7 +359,7 @@
};
};
usbotg_hs_pins_a: usbotg_hs-0 {
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};

26
fdts/stm32mp151.dtsi
View File

@ -174,7 +174,7 @@
};
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
@ -319,7 +319,7 @@
status = "disabled";
};
sdmmc1: sdmmc@58005000 {
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
@ -334,7 +334,7 @@
status = "disabled";
};
sdmmc2: sdmmc@58007000 {
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
@ -358,6 +358,24 @@
status = "disabled";
};
ddr: ddr@5a003000{
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550 0x5A004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
@ -434,7 +452,7 @@
status = "disabled";
};
bsec: nvmem@5c005000 {
bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;

27
fdts/stm32mp157c-ed1.dts
View File

@ -20,7 +20,6 @@
stdout-path = "serial0:115200n8";
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
@ -52,7 +51,7 @@
};
&cryp1 {
status="okay";
status = "okay";
};
&hash1 {
@ -233,7 +232,7 @@
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
@ -269,25 +268,33 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = <2 80 0 0 0 PQR(1,0,0)>;
frac = <0x800>;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = <2 65 1 0 0 PQR(1,1,1)>;
frac = <0x1400>;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = <1 33 1 16 36 PQR(1,1,1)>;
frac = <0x1a04>;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = <3 98 5 7 7 PQR(1,1,1)>;
};
};

3
fdts/stm32mp157c-ev1.dts
View File

@ -57,6 +57,7 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
pinctrl-0 = <&usart3_pins_b>;
uart-has-rtscts;
status = "disabled";
};

16
fdts/stm32mp157c-lxa-mc1.dts
View File

@ -75,7 +75,7 @@
&sdmmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_b4_pins_a &mc1_sdmmc2_d47_pins_b>;
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
bus-width = <8>;
no-1-8-v;
no-sd;
@ -91,17 +91,3 @@
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
&pinctrl {
mc1_sdmmc2_d47_pins_b: mc1-sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
};

7
fdts/stm32mp15xx-dkx.dtsi
View File

@ -141,7 +141,6 @@
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdda: ldo5 {
@ -223,7 +222,7 @@
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
@ -319,13 +318,13 @@
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_b>;
pinctrl-0 = <&uart7_pins_c>;
status = "disabled";
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_b>;
pinctrl-0 = <&usart3_pins_c>;
uart-has-rtscts;
status = "disabled";
};

2
fdts/stm32mp15xxaa-pinctrl.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&pinctrl {

2
fdts/stm32mp15xxab-pinctrl.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&pinctrl {

2
fdts/stm32mp15xxac-pinctrl.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&pinctrl {

2
fdts/stm32mp15xxad-pinctrl.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&pinctrl {