From ff7b75e213e4fe575d5f58f30fe3a1a63fe8ce0b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 10 Dec 2020 22:17:58 -0600 Subject: [PATCH] ti: k3: Move USE_COHERENT_MEM only for the generic board commit 65f7b81728d0 ("ti: k3: common: Use coherent memory for shared data") introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to handle multiple clusters across L3 cache systems. This is represented by "generic" board in k3 platform. On "lite" platforms, however, system level coherency is lacking since we don't have a global monitor or an L3 cache controller. Though, at a cluster level, ARM CPU level coherency is very much possible since the max number of clusters permitted in lite platform configuration is "1". However, we need to be able to disable USE_COHERENT_MEM for the lite configuration due to the lack of system level coherency. See docs/getting_started/build-options.rst for further information. Signed-off-by: Nishanth Menon Change-Id: I4a0ec150b3f9ea12369254aef834a6cbe82d6be6 --- plat/ti/k3/board/generic/board.mk | 3 +++ plat/ti/k3/common/plat_common.mk | 3 +-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk index a34221454..c5bd1ec3c 100644 --- a/plat/ti/k3/board/generic/board.mk +++ b/plat/ti/k3/board/generic/board.mk @@ -13,5 +13,8 @@ $(eval $(call add_define,PRELOADED_BL33_BASE)) K3_HW_CONFIG_BASE ?= 0x82000000 $(eval $(call add_define,K3_HW_CONFIG_BASE)) +# System coherency is managed in hardware +USE_COHERENT_MEM := 1 + PLAT_INCLUDES += \ -Iplat/ti/k3/board/generic/include \ diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 05c004993..ab7366b7e 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -11,9 +11,8 @@ COLD_BOOT_SINGLE_CPU := 1 # We can choose where a core starts executing PROGRAMMABLE_RESET_ADDRESS:= 1 -# System coherency is managed in hardware +# ARM coherency is managed in hardware WARMBOOT_ENABLE_DCACHE_EARLY := 1 -USE_COHERENT_MEM := 1 # A53 erratum for SoC. (enable them all) ERRATA_A53_826319 := 1