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Merge "TZ DMC620 driver: Fix MISRA-2012 defects" into integration

This commit is contained in:
Mark Dykes 2020-07-27 21:30:29 +00:00 committed by TrustedFirmware Code Review
parent f5d9d89593 858e69e85e
commit ffef797d89
2 changed files with 23 additions and 22 deletions
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35
drivers/arm/tzc/tzc_dmc620.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -17,7 +17,7 @@
/* Helper macro for getting dmc_base addr of a dmc_inst */ /* Helper macro for getting dmc_base addr of a dmc_inst */
#define DMC_BASE(plat_data, dmc_inst) \ #define DMC_BASE(plat_data, dmc_inst) \
((uintptr_t)(plat_data->dmc_base[dmc_inst])) ((uintptr_t)((plat_data)->dmc_base[(dmc_inst)]))
/* Pointer to the tzc_dmc620_config_data structure populated by the platform */ /* Pointer to the tzc_dmc620_config_data structure populated by the platform */
static const tzc_dmc620_config_data_t *g_plat_config_data; static const tzc_dmc620_config_data_t *g_plat_config_data;
@ -31,8 +31,7 @@ static const tzc_dmc620_config_data_t *g_plat_config_data;
static void tzc_dmc620_validate_plat_driver_data( static void tzc_dmc620_validate_plat_driver_data(
const tzc_dmc620_driver_data_t *plat_driver_data) const tzc_dmc620_driver_data_t *plat_driver_data)
{ {
uint8_t dmc_inst, dmc_count; unsigned int dmc_inst, dmc_count, dmc_id;
unsigned int dmc_id;
uintptr_t base; uintptr_t base;
assert(plat_driver_data != NULL); assert(plat_driver_data != NULL);
@ -59,7 +58,7 @@ static void tzc_dmc620_configure_region(int region_no,
{ {
uint32_t min_31_00, min_47_32; uint32_t min_31_00, min_47_32;
uint32_t max_31_00, max_47_32; uint32_t max_31_00, max_47_32;
uint8_t dmc_inst, dmc_count; unsigned int dmc_inst, dmc_count;
uintptr_t base; uintptr_t base;
const tzc_dmc620_driver_data_t *plat_driver_data; const tzc_dmc620_driver_data_t *plat_driver_data;
@ -67,19 +66,19 @@ static void tzc_dmc620_configure_region(int region_no,
assert(plat_driver_data != NULL); assert(plat_driver_data != NULL);
/* Do range checks on regions. */ /* Do range checks on regions. */
assert((region_no >= 0U) && (region_no <= DMC620_ACC_ADDR_COUNT)); assert((region_no >= 0) && (region_no <= DMC620_ACC_ADDR_COUNT));
/* region_base and (region_top + 1) must be 4KB aligned */ /* region_base and (region_top + 1) must be 4KB aligned */
assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U); assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U);
dmc_count = plat_driver_data->dmc_count; dmc_count = plat_driver_data->dmc_count;
for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) { for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) {
min_31_00 = (region_base & MASK_31_16) | sec_attr; min_31_00 = (uint32_t)((region_base & MASK_31_16) | sec_attr);
min_47_32 = (region_base & MASK_47_32) min_47_32 = (uint32_t)((region_base & MASK_47_32)
>> DMC620_ACC_ADDR_WIDTH; >> DMC620_ACC_ADDR_WIDTH);
max_31_00 = (region_top & MASK_31_16); max_31_00 = (uint32_t)(region_top & MASK_31_16);
max_47_32 = (region_top & MASK_47_32) max_47_32 = (uint32_t)((region_top & MASK_47_32)
>> DMC620_ACC_ADDR_WIDTH; >> DMC620_ACC_ADDR_WIDTH);
/* Extract the base address of the DMC-620 instance */ /* Extract the base address of the DMC-620 instance */
base = DMC_BASE(plat_driver_data, dmc_inst); base = DMC_BASE(plat_driver_data, dmc_inst);
@ -100,7 +99,7 @@ static void tzc_dmc620_configure_region(int region_no,
*/ */
static void tzc_dmc620_set_action(void) static void tzc_dmc620_set_action(void)
{ {
uint8_t dmc_inst, dmc_count; unsigned int dmc_inst, dmc_count;
uintptr_t base; uintptr_t base;
const tzc_dmc620_driver_data_t *plat_driver_data; const tzc_dmc620_driver_data_t *plat_driver_data;
@ -123,7 +122,7 @@ static void tzc_dmc620_set_action(void)
*/ */
static void tzc_dmc620_verify_complete(void) static void tzc_dmc620_verify_complete(void)
{ {
uint8_t dmc_inst, dmc_count; unsigned int dmc_inst, dmc_count;
uintptr_t base; uintptr_t base;
const tzc_dmc620_driver_data_t *plat_driver_data; const tzc_dmc620_driver_data_t *plat_driver_data;
@ -133,8 +132,9 @@ static void tzc_dmc620_verify_complete(void)
/* Extract the base address of the DMC-620 instance */ /* Extract the base address of the DMC-620 instance */
base = DMC_BASE(plat_driver_data, dmc_inst); base = DMC_BASE(plat_driver_data, dmc_inst);
while ((mmio_read_32(base + DMC620_MEMC_STATUS) & while ((mmio_read_32(base + DMC620_MEMC_STATUS) &
DMC620_MEMC_CMD_MASK) != DMC620_MEMC_CMD_GO) DMC620_MEMC_CMD_MASK) != DMC620_MEMC_CMD_GO) {
continue; continue;
}
} }
} }
@ -145,7 +145,7 @@ static void tzc_dmc620_verify_complete(void)
*/ */
void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data) void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data)
{ {
int i; uint8_t i;
/* Check if valid pointer is passed */ /* Check if valid pointer is passed */
assert(plat_config_data != NULL); assert(plat_config_data != NULL);
@ -164,11 +164,12 @@ void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data)
g_plat_config_data = plat_config_data; g_plat_config_data = plat_config_data;
INFO("Configuring DMC-620 TZC settings\n"); INFO("Configuring DMC-620 TZC settings\n");
for (i = 0U; i < g_plat_config_data->acc_addr_count; i++) for (i = 0U; i < g_plat_config_data->acc_addr_count; i++) {
tzc_dmc620_configure_region(i, tzc_dmc620_configure_region(i,
g_plat_config_data->plat_acc_addr_data[i].region_base, g_plat_config_data->plat_acc_addr_data[i].region_base,
g_plat_config_data->plat_acc_addr_data[i].region_top, g_plat_config_data->plat_acc_addr_data[i].region_top,
g_plat_config_data->plat_acc_addr_data[i].sec_attr); g_plat_config_data->plat_acc_addr_data[i].sec_attr);
}
tzc_dmc620_set_action(); tzc_dmc620_set_action();
tzc_dmc620_verify_complete(); tzc_dmc620_verify_complete();

10
include/drivers/arm/tzc_dmc620.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -32,16 +32,16 @@
/* Address offsets of access address next registers */ /* Address offsets of access address next registers */
#define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \ #define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \
(DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \ (DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \
(region_no * DMC620_ACC_ADDR_NEXT_SIZE)) ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
#define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \ #define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \
(DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \ (DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \
(region_no * DMC620_ACC_ADDR_NEXT_SIZE)) ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
#define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \ #define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \
(DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \ (DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \
(region_no * DMC620_ACC_ADDR_NEXT_SIZE)) ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
#define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \ #define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \
(DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \ (DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \
(region_no * DMC620_ACC_ADDR_NEXT_SIZE)) ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
/* Number of TZC address regions in DMC-620 */ /* Number of TZC address regions in DMC-620 */
#define DMC620_ACC_ADDR_COUNT U(8) #define DMC620_ACC_ADDR_COUNT U(8)