Commit Graph

10773 Commits

Author SHA1 Message Date
Madhukar Pappireddy 1d41fffff7 Merge "docs(versal): fix the versal platform emu name" into integration 2022-05-12 16:49:36 +02:00
Madhukar Pappireddy b57ccdf918 Merge "fix(errata): workaround for DSU-110 erratum 2313941" into integration 2022-05-12 16:34:40 +02:00
Madhukar Pappireddy 868f9768bb Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
  fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
  fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
  fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
  fix(intel): extending to support large file size for AES encryption and decryption
  feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
  feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
  fix(intel): update certificate mask for FPGA Attestation
  feat(intel): update to support maximum response data size
  feat(intel): support ECDSA HASH Verification
  feat(intel): support ECDSA HASH Signing
  feat(intel): support ECDH request
  feat(intel): support ECDSA SHA-2 Data Signature Verification
  feat(intel): support ECDSA SHA-2 Data Signing
  feat(intel): support ECDSA Get Public Key
  feat(intel): support session based SDOS encrypt and decrypt
  feat(intel): support AES Crypt Service
  feat(intel): support HMAC SHA-2 MAC verify request
  feat(intel): support SHA-2 hash digest generation on a blob
  feat(intel): support extended random number generation
  feat(intel): support crypto service key operation
  feat(intel): support crypto service session
  feat(intel): extend attestation service to Agilex family
  fix(intel): flush dcache before sending certificate to mailbox
  fix(intel): introduce a generic response error code
  fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
  feat(intel): single certificate feature enablement
  feat(intel): initial commit for attestation service
  fix(intel): update encryption and decryption command logic
2022-05-12 16:19:15 +02:00
Madhukar Pappireddy 1f0309d498 Merge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration 2022-05-12 16:14:55 +02:00
Manish Pandey 6c87abdda4 fix(arm): remove reclamation of functions starting with "init"
When RECLAIM_INIT_CODE is enabled, functions with __init attribute can
be reclaimed after boot and marked as Execute Never.
Because of a bug in linker script the functions starting with "init"
were also marked XN and causing instruction abort.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2221973c05af170acf4e723cd44645b9ff9d58d2
2022-05-12 14:21:28 +01:00
Bipin Ravi c2a15217c3 fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex Makalu/Makalu-ELP/Hunter
and Neoverse Demeter/Poseidon.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f6689b662ecac92491e0c0902df4270051ce5b
2022-05-11 19:05:48 +02:00
Bipin Ravi 7e3273e8e4 fix(errata): workaround for DSU-110 erratum 2313941
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions
r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open.

The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable
clock gating of the SCLK domain. This will increase the idle power
consumption.

This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1781796/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2022-05-11 19:05:36 +02:00
Nishant Sharma 18fa43f753 feat(sgi): enable fpregs context save and restore
This is required to prevent Nwd context corruption during StMM
execution.

Standalone MM uses OpenSSL for secure boot, which uses FP registers for
floating point calculations.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I6ed11d4fa5d64c3089a24b66fd048a841c480792
2022-05-11 17:18:21 +01:00
Nishant Sharma 15dd6f19da feat(spm_mm): add support to save and restore fp regs
Add the support to save Nwd's floating point registers before switching
to SEL0 and then restore it after coming out of it. Emit a warning
message if SPM_MM is built with CTX_INCLUDE_FPREGS == 0

There is no need to save FP registers of SEL0 because secure partitions
run to completion.

This change is used to prevent context corruption if secure partition
enabled and Nwd decide to use floating point registers.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I1eea16ea2311a4f00a806ea72c118752821b9abb
2022-05-11 17:18:21 +01:00
Madhukar Pappireddy 15ff61f5ce Merge changes from topic "fix_st_spi" into integration
* changes:
  fix(st-spi): remove SR_BUSY bit check before sending command
  fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
2022-05-11 17:31:44 +02:00
Madhukar Pappireddy bf61c4f0af Merge "docs: update release and code freeze dates" into integration 2022-05-11 17:16:48 +02:00
Bipin Ravi 401cb4bb76 Merge "fix(security): workaround for CVE-2022-23960 for Cortex-X1" into integration 2022-05-11 16:59:15 +02:00
Bipin Ravi c8c7c47bb3 Merge "fix(errata): workarounds for cortex-x1 errata" into integration 2022-05-11 16:59:00 +02:00
Bipin Ravi 123cebe5db Merge "feat(cpu): add support for Cortex-X1" into integration 2022-05-11 16:58:50 +02:00
Tamas Ban c44e50b725 feat(plat/arm/fvp): enable RSS backend based measured boot
Enable the RSS backend based measured boot feature.
In the absence of RSS the mocked version of PSA APIs
are used. They always return with success and hard-code data.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I7543e9033a7a21f1b836d911d8d9498c6e09b956
2022-05-11 15:47:32 +02:00
Tamas Ban 0ce2072d9b feat(lib/psa): mock PSA APIs
Introduce PLAT_RSS_NOT_SUPPORTED build config to
provide a mocked version of PSA APIs. The goal is
to test the RSS backend based measured boot and
attestation token request integration on such
a platform (AEM FVP) where RSS is otherwise
unsupported. The mocked PSA API version does
not send a request to the RSS, it only returns
with success and hard-coded values.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ice8d174adf828c1df08fc589f0e17abd1e382a4d
2022-05-11 15:47:30 +02:00
Tamas Ban 0442ebd2e9 feat(drivers/measured_boot): add RSS backend
Runtime Security Subsystem (RSS) provides for the host:
- Runtime service to store measurments, which were
  computed by the host during measured boot.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia9e4e8a1fe8f01a28da1fd8c434b780f2a08f94e
2022-05-11 15:47:02 +02:00
Tamas Ban ce0c40edc9 feat(drivers/arm/rss): add RSS communication driver
This commit adds a driver to conduct the AP's communication
with the Runtime Security Subsystem (RSS).
RSS is Arm's reference implementation for the CCA HES [1].
It can be considered as a secure enclave to which, for example,
certain services can be offloaded such as initial attestation.

RSS comms driver:
 - Relies on MHU v2.x communication IP, using a generic MHU API,
 - Exposes the psa_call(..) API to the upper layers.

[1] https://developer.arm.com/documentation/DEN0096/latest

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ib174ac7d1858834006bbaf8aad0eb31e3a3ad107
2022-05-11 15:47:02 +02:00
Tamas Ban 084856513d feat(lib/psa): add initial attestation API
Supports:
 - Get Platform Attestation token from secure enclave

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Icaeb7b4eaff08e10f449fbf752068de3ac7974bf
2022-05-11 15:47:02 +02:00
Tamas Ban 758c64715b feat(lib/psa): add measured boot API
A secure enclave could provide an alternate
backend for measured boot. This API can be used
to store measurements in a secure enclave, which
provides the measured boot runtime service.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2448e324e7ece6b318403c5937dfe7abea53d0f3
2022-05-11 15:47:02 +02:00
Tamas Ban af26d7d6f0 feat(drivers/arm/mhu): add MHU driver
The Arm Message Handling Unit (MHU) is a mailbox controller used to
communicate with other processing element(s). Adding a driver to
enable the communication:
- Adding generic MHU driver interface,
- Adding MHU_v2_x driver.

Driver supports:
 - Discovering available MHU channels,
 - Sending / receiving words over MHU channels,
 - Signaling happens over a dedicated channel.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: I41a5b968f6b8319cdbdf7907d70bd8837839862e
2022-05-11 15:47:02 +02:00
Okash Khawaja e81e999b9d fix(security): workaround for CVE-2022-23960 for Cortex-X1
Implements the loop workaround for Cortex-X1.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7
2022-05-11 15:24:37 +02:00
Okash Khawaja 7b76c20d8e fix(errata): workarounds for cortex-x1 errata
This patch adds workarounds for following cortex-x1 errata:

- 1821534 (CatB)
- 1688305 (CatB)
- 1827429 (CatB)

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401782/latest

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I10ebe8d5c56a6d273820bb2c682f21bf98daa7a5
2022-05-11 15:24:29 +02:00
Okash Khawaja 6e8eca78e5 feat(cpu): add support for Cortex-X1
This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I4a3d50a98bf55a555bfaefeed5c7b88a35e3bc21
2022-05-11 15:24:20 +02:00
Daniel Boulby 06c6f6536f docs: update release and code freeze dates
Change-Id: I72d200a0cfbcb4ef53b732faa5b7125dce91395d
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-05-11 11:59:14 +01:00
Sieu Mun Tang ac097fdf07 fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
This patch is to add flash dcache after return
response in INTEL_SIP_SMC_MBOX_SEND_CMD.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie9451e352f2b7c41ebb44a1f6be9da35f4600fb9
2022-05-11 17:46:00 +08:00
Sieu Mun Tang 70a7e6af95 fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
This patch is to extend to support large file size
for SHA2/HMAC get digest and verifying. The large
file will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1815deeb61287b32c3e77c5ac1b547b79ef12674
2022-05-11 17:45:57 +08:00
Sieu Mun Tang 1d97dd74cd fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
This patch is to extend to support large file size
for SHA-2 ECDSA data signing and signature verifying.
The large file will be split into smaller chunk and
send using initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If277b2b375a404fe44b0858006c8ba6316a5ce23
2022-05-11 17:45:55 +08:00
Sieu Mun Tang dcb144f1fb fix(intel): extending to support large file size for AES encryption and decryption
This patch is to extend to support large file size
for AES encryption and decryption. The large file
will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie2ceaf247e0d7082aad84faf399fbd18d129c36a
2022-05-11 17:45:50 +08:00
Sieu Mun Tang c436707bc6 feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
A separated SMC function ID of mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7996d5054f76c139b5ad55451c373f5669a1017f
2022-05-11 17:45:37 +08:00
Sieu Mun Tang ad47f1422f feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29
2022-05-11 17:43:16 +08:00
Boon Khai Ng fe5637f27a fix(intel): update certificate mask for FPGA Attestation
Update the certificate mask to 0xff to cover all certificate
in Agilex family.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b
2022-05-11 16:57:37 +08:00
Sieu Mun Tang b703facaaa feat(intel): update to support maximum response data size
Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe
2022-05-11 16:57:34 +08:00
Sieu Mun Tang 7e25eb8701 feat(intel): support ECDSA HASH Verification
Supporting the command to send digital signature verification
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic86f531bfe7cc7606699f2b064ac677aaf806a76
2022-05-11 16:57:31 +08:00
Sieu Mun Tang 692541051b feat(intel): support ECDSA HASH Signing
Supporting the command to send digital signature signing
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38
2022-05-11 16:57:29 +08:00
Sieu Mun Tang 49446866a5 feat(intel): support ECDH request
This command sends the request on generating a share secret on
Diffie-Hellman key exchange.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7c8470cf036ea8c17bf87401f49936950b3e1d6
2022-05-11 16:57:25 +08:00
Sieu Mun Tang 583050607e feat(intel): support ECDSA SHA-2 Data Signature Verification
This command support ECC based signature verification on a blob.
Supported ECC algorithm are NISP P-256, NISP P-384, Brainpool 256
and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7f43d2a69bbe6693ec1bb90f32b817cf00f9f5ae
2022-05-11 16:57:23 +08:00
Sieu Mun Tang 07912da1b7 feat(intel): support ECDSA SHA-2 Data Signing
This command support ECC based signing on a blob. Supported ECC algorithm
are NISP P-256, NISP P-384, Brainpool 256 and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82f95ddafa6b62f8cd882fce9a3e63e469c85067
2022-05-11 16:57:20 +08:00
Sieu Mun Tang d2fee94afa feat(intel): support ECDSA Get Public Key
To support the ECDSA feature and send the command
as a request to get the public key

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9d7bb5b6ab8ef7d4f3ceb21ff0068baf3175a1ac
2022-05-11 16:57:17 +08:00
Sieu Mun Tang 537ff05257 feat(intel): support session based SDOS encrypt and decrypt
Extends existing Secure Data Object Service (SDOS) encryption and
decryption mailbox command to include session id and context id. The
new format requires an opened crypto service session.

A separated SMC function ID is introduced for the new format and it is
only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I2627750e8337c1af66217e9cb45981a9e06e7d19
2022-05-11 16:57:13 +08:00
Sieu Mun Tang 6726390eb0 feat(intel): support AES Crypt Service
Enable Support for AES Crypt Service to send request
to encrypt or decrypt a blob. Command will send a memory
location that SDM will read and also memory location that
SDM will write back after encryption or decryption operation.
Response will be sent back after the crypto operation is done,
and data is written back to the destination

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86ea4ff64dda2fbb1000591e30fa8cb2640ce954
2022-05-11 16:57:11 +08:00
Sieu Mun Tang c05ea29690 feat(intel): support HMAC SHA-2 MAC verify request
This command sends request on checking the integrity and authenticity
of a blob by comparing the calculated MAC with tagged MAC. The
comparison result will be returned in response.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifefdf67f088d7612d2ec2459d71faf2ec8181222
2022-05-11 16:57:08 +08:00
Sieu Mun Tang 7e8249a2db feat(intel): support SHA-2 hash digest generation on a blob
This command is to request the SHA-2 hash digest on a blob.
If input has a key, the output shall be key-hash digest.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I08cb82d89a8e8f7bfe04f5f01e079ea49fe38cf5
2022-05-11 16:57:02 +08:00
Sieu Mun Tang 24f9dc8a43 feat(intel): support extended random number generation
The random number generation (RNG) mailbox command format
is updated to extends the support to upto 4080 bytes random
number generation. The new RNG format requires an opened
crypto service session.

A separated SMC function ID is introduced for the new RNG
format and it is only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432
2022-05-11 16:56:45 +08:00
Marc Bonnici ce5b35c573 docs(maintainers): introduce SPMC maintainer section
Renamed the existing SPM entry to the SPMD and add myself
as the SPMC maintainer.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic74659b119986df5fc229a4470049d289eeef21a
2022-05-11 09:53:40 +01:00
Venkatesh Yadav Abbarapu 103bbd5624 docs(versal): fix the versal platform emu name
Fix the versal platform emu itr6 name.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id9f3272c85513d8258fbbb3bd719c032053b3ada
2022-05-11 13:46:28 +05:30
Christophe Kerello 5993b9157f fix(st-spi): remove SR_BUSY bit check before sending command
Waiting for SR_BUSY bit when receiving a new command is not needed.
SR_BUSY bit is already managed in the previous command treatment.

Change-Id: I736e8488d354cb165ae765022d864cca1dbdc9ee
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
2022-05-11 10:01:33 +02:00
Christophe Kerello 55de58323e fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.

SR_TCF flags is set when programmed number of bytes have been
transferred to the memory device ("bytes" comprised command and data
send to the SPI device).
So even if there is no data, we must check SR_TCF flag.

Change-Id: I99c4145e639c1b842feb3690dd78329179c18132
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
2022-05-11 10:01:17 +02:00
Sieu Mun Tang 342a0618c7 feat(intel): support crypto service key operation
Support crypto service key operation mailbox commands through SMC.

Crypto service key operation begin by sending an open crypto service
session request to SDM firmware. Once successfully open the session,
send crypto service key management commands (import, export, remove
and get key info) with the associated session id to SDM firmware.
The crypto service key is required before perform any crypto service
(encryption, signing, etc). Last, close the session after finishes
crypto service. All crypto service keys associated with this session
will be erased by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I02406533f38b9607eb1ec7e1395b9dc2d084a9e3
2022-05-11 10:06:41 +08:00
Sieu Mun Tang 6dc00c24ab feat(intel): support crypto service session
Support crypto service open and close session mailbox commands through
SMC.

Crypto service support begin by sending an open crypto service session
request to SDM firmware. Last, close the session after finishes crypto
service. All crypto service parameters with this session will be erased
by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I48968498bbd6f2e71791f4ed38dd5f369e171082
2022-05-11 10:06:37 +08:00