Commit Graph

10771 Commits

Author SHA1 Message Date
Harrison Mutai f1cbbd6332 fix(bl1): invalidate SP in data cache during secure SMC
Invalidate the SP holding `smc_ctx_t` prior to enabling the data cache
when handling SMCs from the secure world. Enabling the data cache
without doing so results in dirty data either being evicted into main
memory, or being used directly from bl1. This corrupted data causes
system failure as the SMC handler attempts to use it.

Change-Id: I5b7225a6fdd1fcfe34ee054ca46dffea06b84b7d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2022-05-18 09:32:08 +01:00
Sandrine Bailleux 48e73457a6 Merge changes from topic "sb/update-maintainers" into integration
* changes:
  docs(maintainers): remove John Powell from code owners
  docs(maintainers): remove Jimmy Brisson from code owners
2022-05-18 07:50:42 +02:00
Madhukar Pappireddy d8701fa5bd Merge "fix(stm32mp1): include assert.h to fix build failure" into integration 2022-05-17 18:42:32 +02:00
Olivier Deprez ee211d0864 Merge "docs: update supported FVP models documentation" into integration 2022-05-17 17:40:45 +02:00
Manish V Badarkhe 570c71b20a fix(stm32mp1): include assert.h to fix build failure
stm32mp1 platform build failed with the error [1] in the coverity, to
fix it included assert.h file.

Including bl32/sp_min/sp_min.mk
plat/st/stm32mp1/plat_image_load.c: In function
'plat_get_bl_image_load_info':
plat/st/stm32mp1/plat_image_load.c:30:2: error: implicit declaration of
function 'assert' [-Werror=implicit-function-declaration]
   30 |  assert(bl33 != NULL);
      |  ^~~~~~
plat/st/stm32mp1/plat_image_load.c:9:1: note: 'assert' is defined in
header '<assert.h>'; did you forget to '#include <assert.h>'?
    8 | #include <plat/common/platform.h>
  +++ |+#include <assert.h>
    9 |
cc1: all warnings being treated as errors

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I486bd695298798c05008158545668020babb3eca
2022-05-17 16:34:02 +01:00
Madhukar Pappireddy a12a2c461b Merge "fix(stm32mp1-fdts): correct memory mapping for STM32MP13" into integration 2022-05-17 17:15:11 +02:00
Manish Pandey d8ba3278c8 Merge "refactor(security): upgrade tools to OpenSSL 3.0" into integration 2022-05-17 16:48:07 +02:00
Maksims Svecovs 173c3afcb4 docs: update supported FVP models documentation
Update supported models list according to changes for v2.7 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: 5c54251
* CSS model update: 3bd12fb

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I38c2ef2991b23873821c7e34ad2900b9ad023c4b
2022-05-17 15:27:22 +01:00
Yann Gautier 99605fb116 fix(stm32mp1-fdts): correct memory mapping for STM32MP13
On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocated to OP-TEE is then 32MB, and the shared memory
does no more appear in the STM32MP13 fw-config DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e9238ddb4d82079b9ddf8fc8f6916b5b989d263
2022-05-17 16:21:25 +02:00
Manish Pandey 4c4315e874 Merge "fix(arm): remove reclamation of functions starting with "init"" into integration 2022-05-17 11:11:16 +02:00
Sandrine Bailleux 652df56626 docs(maintainers): remove John Powell from code owners
John Powell is no longer part of the TF-A core team at Arm.

Change-Id: Iaa91474cb2c5c334b9ae6f2376724fad2677e285
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:34:15 +02:00
Sandrine Bailleux 9293278c4b docs(maintainers): remove Jimmy Brisson from code owners
Jimmy Brisson is no longer part of the TF-A core team at Arm.

Change-Id: I2966c513a0c2cda438a05dedd42149d16190cbf6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:26:55 +02:00
Sandrine Bailleux 1b7c82cafe docs(threat-model): remove some redundant text in threat #08
The threat description was repeating the threat title.

Change-Id: I67de2c0aab6e86bf33eb91e7562e075fcb76259b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 50075fdcfb build(changelog): add new scope for the threat model
Change-Id: I884f31f7f4b5515c420839ff37d401faa69f5fff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 3d6cc21066 docs(threat-model): revamp threat #9
Reword the description of threat #9 to make it more future-proof for
Arm CCA. By avoiding specific references to secure or non-secure
contexts, in favour of "worlds" and "security contexts", we make the
description equally applicable to 2-world and 4-world architectures.

Note that there are other threats that would benefit from such a
similar revamp but this is out of scope of this patch.

Also list malicious secure world code as a potential threat
agent. This seems to be an oversight in the first version of the
threat model (i.e. this change is not related to Arm CCA).

Change-Id: Id8c8424b0a801104c4f3dc70e344ee702d2b259a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 4365b30ccf docs(threat-model): make experimental features out of scope
By nature, experimental features are incomplete pieces of work,
sometimes going under rapid change. Typically, the threat model
implications have not been fully considered yet.

Change-Id: Ice8d4273a789558e912f82cde592da4747b37fdf
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux f10dd3e039 docs(threat-model): cosmetic changes
- Add empty lines after titles.

 - Reduce number of highlighting characters to fit title length.

 - Remove most ``monospaced text``.
   I think most of it looked weird in the rendered HTML version and
   it had no obvious meaning.

Change-Id: I5f746a3de035d8ac59eec0af491c187bfe86dad7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Venkatesh Yadav Abbarapu 944e7ea94f fix(zynqmp): resolve misra 8.3 warnings
MISRA Violation: MISRA-C:2012 R.8.3
- Declaration uses a different parameter name than the one present in the
definition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id0521afd7383df13870710b7dd2894e788896e5e
2022-05-17 09:30:21 +05:30
Madhukar Pappireddy 420c400a89 Merge changes I2fcf13b7,I153ccb43 into integration
* changes:
  feat(n1sdp): add support for nt_fw_config
  feat(n1sdp): enable trusted board boot on n1sdp
2022-05-16 21:59:08 +02:00
Juan Pablo Conde 9bc52d330f refactor(security): upgrade tools to OpenSSL 3.0
Host tools cert_tool and encrypt_fw refactored to be fully
compatible with OpenSSL v3.0.

Changes were made following the OpenSSL 3.0 migration guide:
https://www.openssl.org/docs/man3.0/man7/migration_guide.html
In some cases, those changes are straightforward and only
a small modification on the types or API calls was needed
(e.g.: replacing BN_pseudo_rand() with BN_rand(). Both identical
since v1.1.0).
The use of low level APIs is now deprecated. In some cases,
the new API provides a simplified solution for our goals and
therefore the code was simplified accordingly (e.g.: generating
RSA keys through EVP_RSA_gen() without the need of handling the
exponent). However, in some cases, a more
sophisticated approach was necessary, as the use of a context
object was required (e.g.: when retrieving the digest value from
an SHA file).

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I978e8578fe7ab3e71307450ebe7e7812fbcaedb6
2022-05-16 19:01:59 +02:00
Venkatesh Yadav Abbarapu 610eeac894 fix(zynqmp): resolve misra R8.4 warnings
MISRA Violation: MISRA-C:2012 R.8.4
- Function definition does not have a visible prototype.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I50a2c1adf2e099217770ac665f135302f990b162
2022-05-16 17:29:04 +05:30
Olivier Deprez b1470ccc92 Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(spmd): allow forwarding of FFA_FRAG_RX/TX calls
  feat(spmc): add support for FFA_SPM_ID_GET
  feat(spmc): add support for forwarding a secure interrupt to the SP
  feat(spmc): add support for FF-A power mgmt. messages in the EL3 SPMC
2022-05-16 12:32:27 +02:00
Olivier Deprez c8113bf77c Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(spmc): enable the SPMC to pass the linear core ID in a register
  feat(spmc): add FFA_RX_RELEASE handler
  feat(spmc): add FFA_RUN handler
  feat(spmc): support FFA_ID_GET ABI
  feat(spmc): add FFA_FEATURES handler
  feat(spmc): add FFA_PARTITION_INFO_GET handler
  feat(spmc): enable handling FF-A RX/TX Mapping ABIs
  docs(maintainers): introduce SPMC maintainer section
2022-05-16 12:05:59 +02:00
Marc Bonnici 642db98407 feat(spmd): allow forwarding of FFA_FRAG_RX/TX calls
Enable the SPMD to forward FFA_FRAG_RX/TX calls between
the normal world and the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I097a48552827a8527dd3efe1155bc601d7cbf887
2022-05-13 17:47:39 +01:00
Marc Bonnici 46872e01f5 feat(spmc): add support for FFA_SPM_ID_GET
Enable a Secure Partition to query the ID assigned to the SPMC.
The SPMD will take care of any calls from the normal world
therefore we should not need to handle this case in the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I97903e920e928df385addbb2d383f24e602bf2db
2022-05-13 17:47:39 +01:00
Madhukar Pappireddy a921da5ed2 Merge changes If2408af3,If485ff27 into integration
* changes:
  feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
  feat(versal): add support to reset SGI
2022-05-13 18:13:33 +02:00
Achin Gupta 729d7793f8 feat(spmc): add support for forwarding a secure interrupt to the SP
This patch adds support for forwarding a secure interrupt that
preempts the normal world to a SP for top-half interrupt handling.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Iaa6e96f4cf8922ba5b6d128a19359df15e44158d
2022-05-13 17:07:13 +01:00
Olivier Deprez 0dc2b51681 Merge changes from topic "ns/save_fpregs_context" into integration
* changes:
  feat(sgi): enable fpregs context save and restore
  feat(spm_mm): add support to save and restore fp regs
2022-05-13 17:28:58 +02:00
Marc Bonnici f0143004e5 feat(spmc): enable the SPMC to pass the linear core ID in a register
Add TF-A implementation defined behaviour to provide the linear core
ID in the x4 register when bringing up an SP.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I6cb215841097b264d252ec0262b0b7272be99d41
2022-05-13 15:51:23 +01:00
Marc Bonnici 59bd2ad83c feat(spmc): add support for FF-A power mgmt. messages in the EL3 SPMC
This patch adds support for forwarding the following PSCI messages
received by the SPMC at EL3 to the S-EL1 SP if the SP has indicated
that it wishes to receive the appropriate message via its manifest.

1. A PSCI CPU_OFF message in response to a cpu hot unplug request
   from the OS.
2. A message to indicate warm boot of a cpu in response to a cpu
   hot plug request from the OS.
3. A PSCI CPU_SUSPEND message in response to a cpu idle event
   initiated from the OS.
4. A message to indicate warm boot of a cpu from a shallow power
   state in response to a cpu resume power event.

This patch also implements the FFA_SECONDARY_EP_REGISTER function to
enable the SP specify its secondary entrypoint.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I375d0655b2c6fc27445facc39213d1d0678557f4
2022-05-13 15:51:23 +01:00
Marc Bonnici f0c25a082f feat(spmc): add FFA_RX_RELEASE handler
Enable a partition to release its RX buffer and the SPMC
to update the appropriate state tracking.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5fb6d92244b5ed5f032269b29b102aa874bf3ae3
2022-05-13 15:51:23 +01:00
Marc Bonnici aad20c85cb feat(spmc): add FFA_RUN handler
Enable the SPMC to handle the FFA_RUN ABI and update
the state tracking accordingly.

Change-Id: I3e8a3fa3ec9b03830055d2fbd6124b8ff1ed4103
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
2022-05-13 15:51:23 +01:00
Marc Bonnici d5fe92350c feat(spmc): support FFA_ID_GET ABI
Allow for a partition to retrieve its own partition ID.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I1a19ac30b86736d818673c239b2f8fd2d6128c06
2022-05-13 15:51:23 +01:00
Marc Bonnici 55a296387b feat(spmc): add FFA_FEATURES handler
Enable the spmc to report the features that it currently supports.
Populated with the currently implemented functionality.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I00e51ded284efd87cd50a0e9416dbc33f22ced85
2022-05-13 15:51:23 +01:00
Marc Bonnici f74e27723b feat(spmc): add FFA_PARTITION_INFO_GET handler
Enable the SPMC to handle calls to FFA_PARTITION_INFO_GET.
This allows the normal world to discover which partitions
are running in the secure world including logical partitions
in EL3.

This implementation supports both the v1.0 and v1.1
implementations of the Partition Info Get Descriptor.
The SPMC populates the appropriate descriptor in the
partitions RX buffer, if requested, according to the
version of FF-A that the caller is using.

Additionally rename the common/uuid UUID_H include guard
due to a conflict with another header file.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0a85f1dae50fae1fe47a3cafb765fbe9f40619e1
2022-05-13 15:51:23 +01:00
Marc Bonnici 1a752245ec feat(spmc): enable handling FF-A RX/TX Mapping ABIs
Enable handling of FFA_RXTX_MAP and FFA_RXTX_UNMAP ABIs
and ensure these buffers are mapped as required to allow
access by the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ifc425f1ee16c90d1d95b6ae4ac9992d6f785227b
2022-05-13 15:51:21 +01:00
Sandrine Bailleux 6aed554954 Merge changes from topic "rss/mboot-attest" into integration
* changes:
  docs(maintainers): add PSA, MHU, RSS comms code owners
  feat(plat/arm/fvp): enable RSS backend based measured boot
  feat(lib/psa): mock PSA APIs
  feat(drivers/measured_boot): add RSS backend
  feat(drivers/arm/rss): add RSS communication driver
  feat(lib/psa): add initial attestation API
  feat(lib/psa): add measured boot API
  feat(drivers/arm/mhu): add MHU driver
2022-05-13 16:15:35 +02:00
Joanna Farley aa69de86f0 Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
* changes:
  fix(intel): remove unused printout
  fix(intel): fix configuration status based on start request
  style(intel): align the sequence in header file
  fix(intel): remove redundant NOC header declarations
2022-05-13 14:29:24 +02:00
David Vincze c671daeeea docs(maintainers): add PSA, MHU, RSS comms code owners
Adding Sandrine Bailleux for the PSA APIs and myself for the
MHU and RSS comms drivers as code owner.

Change-Id: Ib948479cc6e46163aae59c938877a2d0bcf91754
Signed-off-by: David Vincze <david.vincze@arm.com>
2022-05-13 11:20:05 +02:00
Sieu Mun Tang 0d19eda0dd fix(intel): remove unused printout
This patch is to remove unused printout.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
2022-05-13 16:46:25 +08:00
Sieu Mun Tang 673afd6f8e fix(intel): fix configuration status based on start request
This patch is to fix configuration status command now returns
the result based on the last config start command made to the
runtime software. The status type can be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1ce4b7b4c741d88de88778f8fbed7dfe83a39fbc
2022-05-13 16:46:20 +08:00
Sieu Mun Tang 762c34a85d style(intel): align the sequence in header file
This patch is to align the sequence of function in header file.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9658aef78b06b744c6c14f95b2821daf5dbb0082
2022-05-13 16:46:17 +08:00
Sieu Mun Tang 58690cd629 fix(intel): remove redundant NOC header declarations
This patch is to remove redundant NOC declarations in
system manager header file. The NOC headers are shareable
across both Stratix 10 and Agilex platforms.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I40ff55eb1d8fe280db1d099d5d1a3c2bf4b4b459
2022-05-13 16:46:12 +08:00
Tanmay Shah fcf6f46931 feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
This call is used to register and reset SGI interrupt.
Before this functionality was performed using IOCTL_REGISTER_SGI
pm_ioctl EEMI call. It's not correct use of PM_IOCTL as it is
not EEMI functionality. Instead this new SMCCC call will be
handled by TF-A specific handler.

Change-Id: If2408af38b889d29a5c584e8eec5f1672eab4fb5
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:41 +02:00
Venkatesh Yadav Abbarapu bf70449ba2 feat(versal): add support to reset SGI
Add "reset" parameter in pm_register_sgi() to reset
SGI number. This will be required if OS wants to reset
SGI number to default state. Caller can reset param to
1 to reset SGI in ATF.

Change-Id: If485ff275df884f74eb67671cac7fa953458afe9
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:03 +02:00
Madhukar Pappireddy 15e498de74 Merge "fix(security): workaround for CVE-2022-23960" into integration 2022-05-12 20:24:10 +02:00
sahil cf85030efe feat(n1sdp): add support for nt_fw_config
This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a
2022-05-12 18:51:53 +02:00
sah01 fe2b37f685 feat(n1sdp): enable trusted board boot on n1sdp
Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e
2022-05-12 18:51:32 +02:00
Madhukar Pappireddy 1d41fffff7 Merge "docs(versal): fix the versal platform emu name" into integration 2022-05-12 16:49:36 +02:00
Madhukar Pappireddy b57ccdf918 Merge "fix(errata): workaround for DSU-110 erratum 2313941" into integration 2022-05-12 16:34:40 +02:00