2 Commits

Author	SHA1	Message	Date
Loh Tien Hock	51f366ac85	plat: intel: Fix faulty DDR calibration value ... A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>	2019-02-13 14:39:31 +08:00
Loh Tien Hock	9d82ef26c6	plat: intel: Add BL2 support for Stratix 10 SoC ... This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>	2019-02-04 16:17:24 +08:00