Commit Graph

584 Commits

Author SHA1 Message Date
Sandrine Bailleux 638d2b5141 compiler_rt: Import lshrdi3.c file
Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __aeabi_llsr() builtin, which is required by a
subsequent patch that uses a logical right shift operator in AArch32.

Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-11-06 15:42:51 +01:00
Sandrine Bailleux ecc35992f3 compiler_rt: Import latest changes on int_lib.h
Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-11-06 15:42:51 +01:00
Antonio Nino Diaz b4cf974a32 libc: Adapt strlcpy to this codebase
Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-02 13:41:33 +00:00
Antonio Nino Diaz b3e9214e96 libc: Import strlcpy from FreeBSD
From commit aafd1cf4235d78ce85b76d7da63e9589039344b3:

- lib/libc/strlcpy.c

Change-Id: Iaa7028fcc26706bdd6ee3f1e4bd55dd5873a30c6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-02 13:41:33 +00:00
Antonio Nino Diaz f8b30ca89b bakery: Fix MISRA defects
Change-Id: I600bc13522ae977db355b6dc5a1695bce39ec130
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-01 14:15:39 +00:00
Antonio Nino Diaz a0fee7474f context_mgmt: Fix MISRA defects
The macro EL_IMPLEMENTED() has been deprecated in favour of the new
function el_implemented().

Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-01 14:15:39 +00:00
Antonio Niño Díaz 3d7ae0b9d6
Merge pull request #1657 from antonio-nino-diaz-arm/an/libfdt
libfdt: Downgrade to version 1.4.6-9
2018-11-01 12:45:32 +01:00
Antonio Nino Diaz 00f588bf2c libfdt: Downgrade to version 1.4.6-9
Version 1.4.7 introduces a big performance hit to functions that access
the FDT. Downgrade the library to version 1.4.6-9, before the changes
that introduce the problem. Version 1.4.6 isn't used because one of the
libfdt files (fdt_overlay.c) is missing the license header. This
problem is also fixed in 1.4.6-9.

This version corresponds to commit <aadd0b65c987> checks: centralize
printing of property names in failure messages.

Fixes ARM-software/tf-issues#643

Change-Id: I73c05f2b1f994bcdcc4366131ce0647553cdcfb8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-30 13:42:13 +00:00
Antonio Nino Diaz 195e363f84 Fix MISRA defects in PMF
No functional changes.

Change-Id: I64abd72026082218a40b1a4b8f7dc26ff2478ba6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-29 14:42:39 +00:00
Antonio Nino Diaz 435349977c Fix MISRA defects in workaround and errata framework
No functional changes.

Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-29 14:41:48 +00:00
Antonio Nino Diaz 40daecc1be Fix MISRA defects in extension libs
No functional changes.

Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-29 14:41:48 +00:00
Soby Mathew 931f7c6156 PIE: Position Independant Executable support for BL31
This patch introduces Position Independant Executable(PIE) support
in TF-A. As a initial prototype, only BL31 can support PIE. A trivial
dynamic linker is implemented which supports fixing up Global Offset
Table(GOT) and Dynamic relocations(.rela.dyn). The fixup_gdt_reloc()
helper function implements this linker and this needs to be called
early in the boot sequence prior to invoking C functions. The GOT is
placed in the RO section of BL31 binary for improved security and the
BL31 linker script is modified to export the appropriate symbols
required for the dynamic linker.

The C compiler always generates PC relative addresses to linker symbols
and hence referencing symbols exporting constants are a problem when
relocating the binary. Hence the reference to the
`__PERCPU_TIMESTAMP_SIZE__` symbol in PMF is removed and is now calculated
at runtime based on start and end addresses.

Change-Id: I1228583ff92cf432963b7cef052e95d995cca93d
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-29 09:54:32 +00:00
Soby Mathew 12af5ed4fb Make errata reporting mandatory for CPU files
Previously the errata reporting was optional for CPU operation
files and this was achieved by making use of weak reference to
resolve to 0 if the symbol is not defined. This is error prone
when adding new CPU operation files and weak references are
problematic when fixing up dynamic relocations. Hence this patch
removes the weak reference and makes it mandatory for the CPU
operation files to define the errata reporting function.

Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-29 09:54:32 +00:00
Soby Mathew f1722b693d PIE: Use PC relative adrp/adr for symbol reference
This patch fixes up the AArch64 assembly code to use
adrp/adr instructions instead of ldr instruction for
reference to symbols. This allows these assembly
sequences to be Position Independant. Note that the
the reference to sizes have been replaced with
calculation of size at runtime. This is because size
is a constant value and does not depend on execution
address and using PC relative instructions for loading
them makes them relative to execution address. Also
we cannot use `ldr` instruction to load size as it
generates a dynamic relocation entry which must *not*
be fixed up and it is difficult for a dynamic loader
to differentiate which entries need to be skipped.

Change-Id: I8bf4ed5c58a9703629e5498a27624500ef40a836
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-29 09:54:31 +00:00
Antonio Nino Diaz 03987d01e9 xlat: Fix compatibility between v1 and v2
There are several platforms using arm_setup_page_tables(), which is
supposed to be Arm platform only. This creates several dependency
problems between platforms.

This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib
v2 makefile. This way it is possible to detect from C code which version
is being used and include the correct header.

The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and
moved to a common folder. This way, when in doubt, this header can be
used to guarantee compatibility, as it includes the correct header based
on XLAT_TABLES_LIB_V2.

This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so
that is now locked in xlat lib v2) and ZynqMP (where it was added as a
workaround).

Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-26 14:55:30 +01:00
Antonio Niño Díaz 799bbb1d82
Merge pull request #1643 from antonio-nino-diaz-arm/an/libfdt
Update libfdt to version 1.4.7
2018-10-24 11:30:18 +02:00
Antonio Niño Díaz 44445ae5d8
Merge pull request #1641 from jeenu-arm/ptrauth
AArch64: Enable lower ELs to use pointer authentication
2018-10-24 11:29:57 +02:00
Antonio Nino Diaz 630b011ffd libfdt: Import version v1.4.7
Change-Id: Iad7adaf0b16a3d086594cb3432210ac2c4e207f8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-23 18:34:40 +01:00
Antonio Nino Diaz b7618c93e6 libfdt: Remove current version
The current version of libfdt (1.4.2) has been modified to integrate it
in this repository. In order to do a clean import it is needed to remove
the current version first.

Change-Id: I2cab8c8e5632280d282fa7a2f2339768a0ad1e0f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-23 18:34:19 +01:00
Antonio Nino Diaz 1a29aba367 libc: Integrate strrchr in libc
Change-Id: I3ddc07cb02d73cd7614af7a5b21827aae155f9a0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-23 18:27:45 +01:00
Antonio Nino Diaz 668afe261d libc: Import strrchr from FreeBSD
Imported from lib/libc/string/strrchr.c from commit:

59fd2fb98e4cc7e9bfc89598e28e21d405fd470c

Change-Id: I898206c6f0372d4d211c149ec0fb9522d0a5b01c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-23 18:27:45 +01:00
Andrew F. Davis 6a655a85c0 ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-16 09:27:53 -05:00
Jeenu Viswambharan 3ff4aaaca4 AArch64: Enable lower ELs to use pointer authentication
Pointer authentication is an Armv8.3 feature that introduces
instructions that can be used to authenticate and verify pointers.

Pointer authentication instructions are allowed to be accessed from all
ELs but only when EL3 explicitly allows for it; otherwise, their usage
will trap to EL3. Since EL3 doesn't have trap handling in place, this
patch unconditionally disables all related traps to EL3 to avoid
potential misconfiguration leading to an unhandled EL3 exception.

Fixes ARM-software/tf-issues#629

Change-Id: I9bd2efe0dc714196f503713b721ffbf05672c14d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-10-16 08:31:13 +01:00
Soby Mathew 3e75ea4d1a
Merge pull request #1624 from glneo/less-cache-flushing
PSCI cache flush and comment fixup
2018-10-12 14:16:57 +01:00
ldts a4065abdfb psci: platform control of SYSTEM_SUSPEND entry
Some platforms can only resume from system suspend from the boot
CPU, hence they should only enter that state from that same core.

The following commit presents an interface that allows the platform to
reject system suspend entry near its very last stage (last CPU).
2018-10-11 12:57:49 +02:00
Andrew F. Davis f996a5f79f PSCI: Do not flush cache when unneeded
When a platform enables its caches before it accesses the
psci_non_cpu_pd_nodes structure then explicit cache maintenance
is not needed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-10 13:07:56 -05:00
Andrew F. Davis c98db6c617 PSCI: Update comment on MMU disablement
The MMU is not disabled in this path, update the comment to
reflect this. Also clarify that both paths call prepare_cpu_pwr_dwn(),
but the second path does stack cache maintenance.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-10 13:07:56 -05:00
Antonio Nino Diaz a5fa5658e8 xlat: Fix checks in mmap_add() and mmap_add_ctx()
Commit 79621f0038 broke sgi575.

It is possible to have a region with 0 as value for the attributes. It
means device memory, read only, secure, executable. This is legitimate
if the code is in flash and the code is executed from there.

This is the case for SGI_MAP_FLASH0_RO, defined in the file
plat/arm/css/sgi/sgi_plat.c.

This problem is solved by checking both size and attributes in xlat v1.
In xlat v2, it is enough to check the granularity, as it can never be 0.

Change-Id: I7be11f1b0e51c4c2ffd560b4a6cdfbf15de2c276
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-08 16:15:21 +01:00
Soby Mathew 7e0a38a4d8
Merge pull request #1603 from antonio-nino-diaz-arm/db/reclaim-init
Reclaim BL31 initialization code memory for runtime data
2018-10-04 14:23:31 +01:00
Soby Mathew 3ed87a496a
Merge pull request #1584 from danielboulby-arm/db/Switches
Ensure the flow through switch statements is clear
2018-10-03 15:36:37 +01:00
Daniel Boulby aff2863fe6 Mark xlat tables initialization code
Mark the xlat tables code only used in BL31 initialization as
__init to be reclaimed once no longer needed

Change-Id: I3106bfd994706a57c578624573bcfa525fbbd3c4
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-10-03 11:48:15 +01:00
Daniel Boulby 87c8513498 Mark BL31 initialization functions
Mark the initialization functions in BL31, such as context management,
EHF, RAS and PSCI as __init so that they can be reclaimed by the
platform when no longer needed

Change-Id: I7446aeee3dde8950b0f410cb766b7a2312c20130
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-10-03 11:47:30 +01:00
Daniel Boulby 79621f0038 xlat: Change check in mmap_add and mmap_add_ctx()
Depending on the build flags it is possible that some of the memory
regions mapped in page table setup could have a size of 0. In this
case we simply want to do nothing but still wish to map the other
regions in the array. Therefore we cannot only use size == 0 as
the termination logic for the loop.

Since an attributes field with value 0 means that the region is
device memory, read only, secure and executable. Device memory
can't be executable, so this combination should never be used
and it is safe to use as a terminator value.

Therefore by changing the termination logic to use attributes
instead of size we prevent terminating the loop when we don't
intend to.

Change-Id: I92fc7f689ab08543497be6be4896dace2ed7b66a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-10-03 11:47:30 +01:00
Antonio Nino Diaz fe199e3bac Remove all other deprecated interfaces and files
Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:53 +01:00
Antonio Nino Diaz 90e0c98373 xlat: Remove deprecated interfaces
Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:53 +01:00
Antonio Nino Diaz 0b81230599 PSCI: Remove deprecated file plat_psci_common.c
Change-Id: I9fd8016527ad7706494f34356fdae8efacef5f72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:52 +01:00
Roberto Vargas 871de5373d PSCI: Remove platform compatibility layer
Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:52 +01:00
Daniel Boulby a08a201430 Ensure the flow through switch statements is clear
Ensure case clauses:
*   Terminate with an unconditional break, return or goto statement.
*   Use conditional break, return or goto statements as long as the end
    of the case clause is unreachable; such case clauses must terminate
    with assert(0) /* Unreachable */ or an unconditional  __dead2 function
    call
*   Only fallthough when doing otherwise would result in less
    readable/maintainable code; such case clauses must terminate with a
    /* Fallthrough */ comment to make it clear this is the case and
    indicate that a fallthrough is intended.

This reduces the chance of bugs appearing due to unintended flow through a
switch statement

Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-09-21 13:14:13 +01:00
Soby Mathew 4728900fa7
Merge pull request #1568 from soby-mathew/sm/fix_ares_err_report
Fix the Cortex-ares errata reporting function name
2018-09-10 12:44:38 +01:00
Soby Mathew 66ec7121bd Fix the Cortex-ares errata reporting function name
This patch fixes the name of the Cortex-ares errata function which was
previously named `cortex_a72_errata_report` which was an error.

Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-09-10 11:51:31 +01:00
Jeenu Viswambharan ca9ffc799c RAS: Fix assert condition
Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-07 16:37:06 +01:00
Jeenu Viswambharan 24dc970915 Add missing barriers to Bakery Locks
With the current implementation, it's possible for a contender to
observe accesses in the Critical Section before acquiring or releasing
the lock. Insert fencing in the locking and release codes to prevent any
reorder.

Fixes ARM-software/tf-issues#609

Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-05 14:39:14 +01:00
Varun Wadekar 6cf8d65f27 cpus: denver: Implement static workaround for CVE-2018-3639
For Denver CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.

This approach permanently mitigates the EL3 software stack only. Other
software components are responsible to enable it for their exception
levels.

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3
and earlier:

*   By setting bit 11 (Disable speculative store buffering) of
    `ACTLR_EL3`

*   By setting bit 9 (Disable speculative memory disambiguation) of
    `ACTLR_EL3`

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4
and later:

*   By setting bit 18 (Disable speculative store buffering) of
    `ACTLR_EL3`

*   By setting bit 17 (Disable speculative memory disambiguation) of
    `ACTLR_EL3`

Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-09-04 17:34:08 -07:00
Varun Wadekar cf3ed0dcc7 cpus: denver: reset power state to 'C1' on boot
Denver CPUs expect the power state field to be reset to 'C1'
during boot. This patch updates the reset handler to reset the
ACTLR_.PMSTATE field to 'C1' state during CPU boot.

Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-09-04 17:33:56 -07:00
Varun Wadekar 1593cae46e denver: use plat_my_core_pos() to get core position
The current functions to disable and enable Dynamic Code Optimizer
(DCO) assume that all denver cores are in the same cluster. They
ignore AFF1 field of the mpidr_el1 register, which leads to
incorect logical core id calculation.

This patch calls the platform handler, plat_my_core_pos(), to get
the logical core id to disable/enable DCO for the core.

Original change by: Krishna Sitaraman <ksitaraman@nvidia.com>

Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-09-04 17:33:32 -07:00
Soby Mathew 100992b531
Merge pull request #1484 from nathan-menhorn/tee-validate-header-603
Update optee_utils.c to fix ARM-software/tf-issues#603
2018-09-03 11:29:11 +01:00
Antonio Nino Diaz d5ccb754af libc: Fix some MISRA defects
No functional changes.

Change-Id: I907aa47565af2a6c435a5560041fd2b59e65c25c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 16:21:59 +01:00
Dimitris Papastamos 7bb907e0d9
Merge pull request #1544 from jwerner-chromium/JW_handle_ea
context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation
2018-08-30 16:09:30 +01:00
Antonio Nino Diaz 3e530d8ea8 backtrace: Print backtrace in assert() and panic()
When any of these functions is called the backtrace will be printed to
the console.

Change-Id: Id60842df824b320c485a9323ed6b80600f4ebe35
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 09:21:53 +01:00
Julius Werner 24f671f3a9 context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation
This patch fixes a bug in the context management code that causes it to
ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always
configure SCR_EL3 to force all external aborts to trap into EL3. The
code used #ifdef to read compile-time option declared with add_define in
the Makefile... however, those options are always defined, they're just
defined to either 0 or 1, so #if is the correct syntax to check for
them. Also update the documentation to match.

This bug has existed since the Nov 2017 commit 76454abf4 (AArch64:
Introduce External Abort handling), which changed the
HANDLE_EA_EL3_FIRST option to use add_define.

Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-08-29 17:16:20 -07:00