arm-trusted-firmware

Commit Graph

Author	SHA1	Message	Date
Usama Arif	e231f3a5f4	a5ds: Hold the secondary cpus in pen rather than panic For the secondary CPUs, hold the cpu in wfe rather then panic. This will be needed when multicore support is added to a5ds as the smc call will write to the hold base and signal an event to power on the secondary CPUs. Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599 Signed-off-by: Usama Arif <usama.arif@arm.com>	2019-09-23 17:02:08 +01:00
Usama Arif	00c7d5aca3	plat/arm: Introduce A5 DesignStart platform. This patch adds support for Cortex-A5 FVP for the DesignStart program. DesignStart aims at providing low cost and fast access to Arm IP. Currently with this patch only the primary CPU is booted and the rest of them wait for an interrupt. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab	2019-07-16 14:13:12 +00:00

Author

SHA1

Message

Date

Usama Arif

e231f3a5f4

a5ds: Hold the secondary cpus in pen rather than panic

For the secondary CPUs, hold the cpu in wfe rather then panic.
This will be needed when multicore support is added to a5ds as
the smc call will write to the hold base and signal an event to
power on the secondary CPUs.

Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599
Signed-off-by: Usama Arif <usama.arif@arm.com>

2019-09-23 17:02:08 +01:00

Usama Arif

00c7d5aca3

plat/arm: Introduce A5 DesignStart platform.

This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.

Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab

2019-07-16 14:13:12 +00:00

2 Commits