Commit Graph

5 Commits

Author SHA1 Message Date
Ying-Chun Liu (PaulLiu) 32d5042204 fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x970000 is the correct value thus we change it back again.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Change-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d
2022-01-12 10:33:27 +08:00
Ying-Chun Liu (PaulLiu) f696843eab feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout
Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and block devices.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I401e48216d67257137351ee4d0b98904a76fa789
2021-09-14 21:42:01 +08:00
Peng Fan 6b63125c41 feat(plat/imx8m): add sdei support for i.MX8MP
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I8308c629448bd8adca9d3d25701adcf0c5a6afc2
2021-06-12 21:53:59 +08:00
Jacky Bai 7f9390d3a3 plat: imx8mp: change the bl31 physical load address
on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4
2021-04-30 12:28:41 +02:00
Jacky Bai a775ef25c3 plat: imx8mp: Add the basic support for i.MX8MP
The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a
2020-07-10 16:19:25 +08:00