Use the PMUFW get_chipid call to obtain IDCODE and version register.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
On ZynqMP the FSBL will configure the system counter. Hence, remove the
initialization of the system counter with hardcoded values from the ATF
and use the setup provided by the bootloader.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Add support to provide silicon id to non-secure
software through SMC.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[ sb
Move zynqmp_get_silicon_id outside of compile guards to avoid build
errors.
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The revision field may change between silicon revisions without changing
the mapping to a part. This avoids errors like:
ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093
NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000
on parts with a newer revision.
Reported-by: Love Kumar <love.kumar@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Love Kumar <love.kumar@xilinx.com>
Provide a function to retrieve the bootmode.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This patch moves the definition for `plat_get_syscnt_freq()`
from arm_bl31_setup.c to arm_common.c. This could be useful
in case a delay timer needs to be installed based on the
generic timer in other BLs.
This patch also modifies the return type for this function
from `uint64_t` to `unsigned long long` within ARM and other
platform files.
Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>