Commit Graph

12 Commits

Author SHA1 Message Date
Sandrine Bailleux 86d8948c78 Doc: Add links to the A53/A57 Errata Notice documents
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores
Software Developers Errata Notice documents in the ARM CPU Specific
Build Macros document.

Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
2016-04-21 13:00:28 +01:00
Sandrine Bailleux adeecf9219 Add support for Cortex-A57 erratum 833471 workaround
Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063
2016-04-21 12:59:59 +01:00
Sandrine Bailleux 072888656d Add support for Cortex-A57 erratum 826977 workaround
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa
2016-04-21 12:59:59 +01:00
Sandrine Bailleux 0b77197baf Add support for Cortex-A57 erratum 829520 workaround
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439
2016-04-21 12:59:59 +01:00
Sandrine Bailleux a8b1c76936 Add support for Cortex-A57 erratum 828024 workaround
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d
2016-04-21 12:59:59 +01:00
Sandrine Bailleux df22d602b6 Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
2016-04-21 09:44:51 +01:00
Sandrine Bailleux d1b2b203a7 Cortex-A57: Add link to software optimization guide
This patch adds a link to the Cortex-A57 Software Optimization Guide
in the ARM CPU Specific Build Macros document to justify the default
value of the A57_DISABLE_NON_TEMPORAL_HINT build flag.

Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
2016-02-18 15:38:18 +00:00
Sandrine Bailleux 54035fc467 Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.

This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.

The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.

Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
2016-02-08 09:31:18 +00:00
Jimmy Huang 6b0d97b24a cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added errata build flags

Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
2015-08-05 19:58:39 +08:00
Sandrine Bailleux 121f2ae7ce Miscellaneous doc fixes for v1.1
Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
2015-02-02 17:46:32 +00:00
Joakim Bech 14a5b346de Create Table of Content links in markdown files
Fixes arm-software/tf-issues#276
2015-01-07 15:01:07 +01:00
Soby Mathew 5541bb3f61 Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.

This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.

Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
2014-10-29 17:39:59 +00:00