arm-trusted-firmware

Commit Graph

Author	SHA1	Message	Date
Hadi Asyrafi	328718f254	intel: Refactor common platform code [1/5] Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d	2019-11-28 12:47:57 +08:00
Loh Tien Hock	9d82ef26c6	plat: intel: Add BL2 support for Stratix 10 SoC This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>	2019-02-04 16:17:24 +08:00

Author

SHA1

Message

Date

Hadi Asyrafi

328718f254

intel: Refactor common platform code [1/5]

Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d

2019-11-28 12:47:57 +08:00

Loh Tien Hock

9d82ef26c6

plat: intel: Add BL2 support for Stratix 10 SoC

This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>

2019-02-04 16:17:24 +08:00

2 Commits