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7 Commits

Author SHA1 Message Date
Madhukar Pappireddy 13ce03aa8a Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration 2022-05-06 19:33:59 +02:00
BenjaminLimJL f65bdf3a54 feat(intel): implement timer init divider via cpu frequency. (#1) 
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
 2022-05-06 17:37:45 +02:00
Sieu Mun Tang bb0fcc7e01 feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC 
SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc
 2022-05-05 23:47:20 +08:00
Hadi Asyrafi 328718f254 intel: Refactor common platform code [1/5] 
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
 2019-11-28 12:47:57 +08:00
Hadi Asyrafi fea24b88e4 intel: stratix10: Fix reliance on hard coded clock information 
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
 2019-08-13 18:20:53 +08:00
Muhammad Hadi Asyrafi Abdul Halim 10e70f87e0 intel: Enable watchdog timer on Intel S10 platform 
Watchdog driver support & enablement during platform setup

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2019-03-21 10:35:24 +08:00
Loh Tien Hock 9d82ef26c6 plat: intel: Add BL2 support for Stratix 10 SoC 
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-04 16:17:24 +08:00