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Author SHA1 Message Date
Etienne Carriere 0147bef523 ARMv7 does not support STL instruction 
Also need to add a SEV instruction in ARMv7 spin_unlock which
is implicit in ARMv8.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
 2017-11-08 13:49:29 +01:00
dp-arm 82cb2c1ad9 Use SPDX license identifiers 
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
 2017-05-03 09:39:28 +01:00
Soby Mathew e33b78a658 AArch32: Add support in TF libraries 
This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support for AArch32 register
arguments. The CPU operations for AEM generic cpu in AArch32
mode is also added.

Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483
 2016-08-10 12:35:46 +01:00