/* * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include #include #include .globl plat_get_my_entrypoint .globl plat_secondary_cold_boot_setup .globl plat_is_my_cpu_primary .globl platform_mem_init .globl plat_my_core_pos .globl plat_fpga_calc_core_pos .globl plat_crash_console_init .globl plat_crash_console_putc .globl plat_crash_console_flush /* ----------------------------------------------------------------------- * Indicate a cold boot for every CPU - warm boot is unsupported for the * holding pen PSCI implementation. * ----------------------------------------------------------------------- */ func plat_get_my_entrypoint mov x0, #0 ret endfunc plat_get_my_entrypoint /* ----------------------------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * ----------------------------------------------------------------------- */ func plat_secondary_cold_boot_setup /* * Poll the CPU's hold entry until it indicates to jump * to the entrypoint address. */ bl plat_my_core_pos lsl x0, x0, #PLAT_FPGA_HOLD_ENTRY_SHIFT ldr x1, =hold_base ldr x2, =fpga_sec_entrypoint poll_hold_entry: ldr x3, [x1, x0] cmp x3, #PLAT_FPGA_HOLD_STATE_GO b.ne 1f ldr x3, [x2] br x3 1: wfe b poll_hold_entry endfunc plat_secondary_cold_boot_setup /* ----------------------------------------------------------------------- * unsigned int plat_is_my_cpu_primary (void); * * Find out whether the current cpu is the primary cpu * ----------------------------------------------------------------------- */ func plat_is_my_cpu_primary mrs x0, mpidr_el1 mov_imm x1, MPIDR_AFFINITY_MASK and x0, x0, x1 cmp x0, #FPGA_PRIMARY_CPU cset w0, eq ret endfunc plat_is_my_cpu_primary func platform_mem_init ret endfunc platform_mem_init func plat_my_core_pos mrs x0, mpidr_el1 b plat_fpga_calc_core_pos endfunc plat_my_core_pos /* ----------------------------------------------------------------------- * unsigned int plat_fpga_calc_core_pos(u_register_t mpidr) * ----------------------------------------------------------------------- */ func plat_fpga_calc_core_pos /* * Check for MT bit in MPIDR, which may be either value for images * running on the FPGA. * * If not set, shift MPIDR to left to make it look as if in a * multi-threaded implementation. */ tst x0, #MPIDR_MT_MASK lsl x3, x0, #MPIDR_AFFINITY_BITS csel x3, x3, x0, eq /* Extract individual affinity fields from MPIDR */ ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS /* Compute linear position */ mov x4, #FPGA_MAX_CPUS_PER_CLUSTER madd x1, x2, x4, x1 mov x5, #FPGA_MAX_PE_PER_CPU madd x0, x1, x5, x0 ret endfunc plat_fpga_calc_core_pos func plat_crash_console_init mov_imm x0, PLAT_FPGA_CRASH_UART_BASE b console_pl011_core_init endfunc plat_crash_console_init func plat_crash_console_putc mov_imm x1, PLAT_FPGA_CRASH_UART_BASE b console_pl011_core_putc endfunc plat_crash_console_putc func plat_crash_console_flush mov_imm x0, PLAT_FPGA_CRASH_UART_BASE b console_pl011_core_flush endfunc plat_crash_console_flush