#
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
# Copyright 2017-2022 NXP Semiconductors
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------

CORE_TYPE	:=	a72

CACHE_LINE	:=	6

# set to GIC400 or GIC500
GIC		:=	GIC500

# set to CCI400 or CCN504 or CCN508
INTERCONNECT	:=	CCN508

# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS		:=	3_2

# TZC IP Details TZC used is TZC380 or TZC400
TZC_ID		:=	TZC400

# CONSOLE Details available is NS16550 or PL011
CONSOLE		:=	PL011

# Select the DDR PHY generation to be used
PLAT_DDR_PHY	:=	PHY_GEN2

PHYS_SYS	:=	64

# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD	:= 0xa000

# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
# Input to CST create_hdr_esbc tool
CSF_HDR_SZ	:= 0x3000

NXP_SFP_VER	:= 3_4

# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM
SEC_MEM_NON_COHERENT	:= yes

# Defining the endianness for NXP ESDHC
NXP_ESDHC_ENDIANNESS	:= LE

# Defining the endianness for NXP SFP
NXP_SFP_ENDIANNESS	:= LE

# Defining the endianness for NXP GPIO
NXP_GPIO_ENDIANNESS	:= LE

# Defining the endianness for NXP SNVS
NXP_SNVS_ENDIANNESS	:= LE

# Defining the endianness for NXP CCSR GUR register
NXP_GUR_ENDIANNESS	:= LE

# Defining the endianness for NXP FSPI register
NXP_FSPI_ENDIANNESS	:= LE

# Defining the endianness for NXP SEC
NXP_SEC_ENDIANNESS	:= LE

# Defining the endianness for NXP DDR
NXP_DDR_ENDIANNESS	:= LE

NXP_DDR_INTLV_256B	:= 1

# OCRAM MAP for BL2
# Before BL2
# 0x18000000 - 0x18009fff -> Used by ROM code
# 0x1800a000 - 0x1800dfff -> CSF header for BL2
# (The above area i.e 0x18000000 - 0x1800dfff is available
#  for DDR PHY images scratch pad region during BL2 run time)
# For FlexSPI boot
# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
# For SD boot
# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
# 0x18030000 - 0x18040000 -> Reserved for SD buffer
OCRAM_START_ADDR := 0x18000000
OCRAM_SIZE := 0x40000

# Location of BL2 on OCRAM
BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
# Covert to HEX to be used by create_pbl.mk
BL2_BASE	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))

# BL2_HDR_LOC is at  (OCRAM_ADDR + NXP_ROM_RSVD)
# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
BL2_HDR_LOC_HDR	?=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) )))
# Covert to HEX to be used by create_pbl.mk
BL2_HDR_LOC	:=	$$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)

# SoC ERRATAS to be enabled
#
# Core Errata
ERRATA_A72_859971	:= 1

# SoC Errata
ERRATA_SOC_A050426	:= 1

# DDR Errata
ERRATA_DDR_A011396	:= 1
ERRATA_DDR_A050450	:= 1
ERRATA_DDR_A050958	:= 1

# enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC :=	1