124 lines
3.2 KiB
C
124 lines
3.2 KiB
C
/*
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "dfx.h"
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#include <mvebu_def.h>
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#include <mvebu.h>
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#include <errno.h>
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/* #define DEBUG_DFX */
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#ifdef DEBUG_DFX
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#define debug(format...) NOTICE(format)
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#else
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#define debug(format, arg...)
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#endif
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#define SAR_BASE (MVEBU_REGS_BASE + 0x6F8200)
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#define SAR_SIZE 0x4
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#define AP_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8240)
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#define JTAG_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8244)
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#define EFUSE_CTRL (MVEBU_REGS_BASE + 0x6F8008)
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#define EFUSE_LD_BASE (MVEBU_REGS_BASE + 0x6F8F00)
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#define EFUSE_LD_SIZE 0x1C
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#define EFUSE_HD_BASE (MVEBU_REGS_BASE + 0x6F9000)
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#define EFUSE_HD_SIZE 0x3F8
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/* AP806 CPU DFS register mapping*/
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#define AP806_CA72MP2_0_PLL_CR_0_BASE (MVEBU_REGS_BASE + 0x6F8278)
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#define AP806_CA72MP2_0_PLL_CR_1_BASE (MVEBU_REGS_BASE + 0x6F8280)
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#define AP806_CA72MP2_0_PLL_CR_2_BASE (MVEBU_REGS_BASE + 0x6F8284)
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#define AP806_CA72MP2_0_PLL_SR_BASE (MVEBU_REGS_BASE + 0x6F8C94)
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/* AP807 CPU DFS register mapping */
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#define AP807_DEVICE_GENERAL_CR_10_BASE (MVEBU_REGS_BASE + 0x6F8278)
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#define AP807_DEVICE_GENERAL_CR_11_BASE (MVEBU_REGS_BASE + 0x6F827C)
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#define AP807_DEVICE_GENERAL_STATUS_6_BASE (MVEBU_REGS_BASE + 0x6F8C98)
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#ifdef MVEBU_SOC_AP807
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#define CLUSTER_OFFSET 0x8
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#define CLK_DIVIDER_REG AP807_DEVICE_GENERAL_CR_10_BASE
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#define CLK_FORCE_REG AP807_DEVICE_GENERAL_CR_11_BASE
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#define CLK_RATIO_REG AP807_DEVICE_GENERAL_CR_11_BASE
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#define CLK_RATIO_STATE_REG AP807_DEVICE_GENERAL_STATUS_6_BASE
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#else
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#define CLUSTER_OFFSET 0x14
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#define CLK_DIVIDER_REG AP806_CA72MP2_0_PLL_CR_0_BASE
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#define CLK_FORCE_REG AP806_CA72MP2_0_PLL_CR_1_BASE
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#define CLK_RATIO_REG AP806_CA72MP2_0_PLL_CR_2_BASE
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#define CLK_RATIO_STATE_REG AP806_CA72MP2_0_PLL_SR_BASE
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#endif /* MVEBU_SOC_AP807 */
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static _Bool is_valid(u_register_t addr)
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{
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switch (addr) {
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case AP_DEV_ID_STATUS_REG:
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case JTAG_DEV_ID_STATUS_REG:
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case SAR_BASE ... (SAR_BASE + SAR_SIZE):
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case EFUSE_LD_BASE ... (EFUSE_LD_BASE + EFUSE_LD_SIZE):
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case EFUSE_HD_BASE ... (EFUSE_HD_BASE + EFUSE_HD_SIZE):
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case EFUSE_CTRL:
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/* cpu-clk related registers */
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case CLK_DIVIDER_REG:
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case CLK_DIVIDER_REG + CLUSTER_OFFSET:
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case CLK_FORCE_REG:
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case CLK_FORCE_REG + CLUSTER_OFFSET:
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#ifndef MVEBU_SOC_AP807
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case CLK_RATIO_REG:
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case CLK_RATIO_REG + CLUSTER_OFFSET:
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#endif
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case CLK_RATIO_STATE_REG:
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case CLK_RATIO_STATE_REG + CLUSTER_OFFSET:
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return true;
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default:
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return false;
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}
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}
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static int armada_dfx_sread(u_register_t *read, u_register_t addr)
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{
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if (!is_valid(addr))
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return -EINVAL;
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*read = mmio_read_32(addr);
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return 0;
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}
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static int armada_dfx_swrite(u_register_t addr, u_register_t val)
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{
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if (!is_valid(addr))
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return -EINVAL;
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mmio_write_32(addr, val);
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return 0;
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}
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int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
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u_register_t addr, u_register_t val)
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{
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debug_enter();
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debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val);
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switch (func) {
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case MV_SIP_DFX_SREAD:
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return armada_dfx_sread(read, addr);
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case MV_SIP_DFX_SWRITE:
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return armada_dfx_swrite(addr, val);
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default:
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ERROR("unsupported dfx misc sub-func\n");
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return -EINVAL;
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}
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debug_exit();
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return 0;
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}
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