152 lines
3.3 KiB
C
152 lines
3.3 KiB
C
/*
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* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/clk.h>
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#include <drivers/st/stm32mp1_ddr.h>
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#include <drivers/st/stm32mp1_ddr_helpers.h>
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#include <drivers/st/stm32mp1_ram.h>
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#include <drivers/st/stm32mp_ddr.h>
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#include <drivers/st/stm32mp_ddr_test.h>
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#include <drivers/st/stm32mp_ram.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include <platform_def.h>
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static struct stm32mp_ddr_priv ddr_priv_data;
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int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed)
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{
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unsigned long ddrphy_clk, ddr_clk, mem_speed_hz;
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ddr_enable_clock();
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ddrphy_clk = clk_get_rate(DDRPHYC);
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VERBOSE("DDR: mem_speed (%u kHz), RCC %lu kHz\n",
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mem_speed, ddrphy_clk / 1000U);
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mem_speed_hz = mem_speed * 1000U;
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/* Max 10% frequency delta */
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if (ddrphy_clk > mem_speed_hz) {
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ddr_clk = ddrphy_clk - mem_speed_hz;
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} else {
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ddr_clk = mem_speed_hz - ddrphy_clk;
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}
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if (ddr_clk > (mem_speed_hz / 10)) {
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ERROR("DDR expected freq %u kHz, current is %lu kHz\n",
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mem_speed, ddrphy_clk / 1000U);
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return -1;
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}
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return 0;
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}
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static int stm32mp1_ddr_setup(void)
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{
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struct stm32mp_ddr_priv *priv = &ddr_priv_data;
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int ret;
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struct stm32mp_ddr_config config;
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int node;
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uint32_t uret;
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void *fdt;
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const struct stm32mp_ddr_param param[] = {
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CTL_PARAM(reg),
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CTL_PARAM(timing),
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CTL_PARAM(map),
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CTL_PARAM(perf),
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PHY_PARAM(reg),
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PHY_PARAM(timing),
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};
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if (fdt_get_address(&fdt) == 0) {
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return -ENOENT;
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}
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node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
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if (node < 0) {
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ERROR("%s: Cannot read DDR node in DT\n", __func__);
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return -EINVAL;
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}
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ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info);
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if (ret < 0) {
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return ret;
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}
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ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config);
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if (ret < 0) {
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return ret;
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}
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/* Disable axidcg clock gating during init */
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mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
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stm32mp1_ddr_init(priv, &config);
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/* Enable axidcg clock gating */
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mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
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priv->info.size = config.info.size;
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VERBOSE("%s : ram size(%x, %x)\n", __func__,
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(uint32_t)priv->info.base, (uint32_t)priv->info.size);
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if (stm32mp_map_ddr_non_cacheable() != 0) {
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panic();
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}
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uret = stm32mp_ddr_test_data_bus();
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if (uret != 0U) {
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ERROR("DDR data bus test: can't access memory @ 0x%x\n",
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uret);
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panic();
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}
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uret = stm32mp_ddr_test_addr_bus(config.info.size);
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if (uret != 0U) {
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ERROR("DDR addr bus test: can't access memory @ 0x%x\n",
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uret);
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panic();
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}
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uret = stm32mp_ddr_check_size();
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if (uret < config.info.size) {
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ERROR("DDR size: 0x%x does not match DT config: 0x%x\n",
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uret, config.info.size);
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panic();
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}
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if (stm32mp_unmap_ddr() != 0) {
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panic();
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}
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return 0;
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}
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int stm32mp1_ddr_probe(void)
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{
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struct stm32mp_ddr_priv *priv = &ddr_priv_data;
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VERBOSE("STM32MP DDR probe\n");
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priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base();
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priv->phy = (struct stm32mp_ddrphy *)stm32mp_ddrphyc_base();
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priv->pwr = stm32mp_pwr_base();
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priv->rcc = stm32mp_rcc_base();
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priv->info.base = STM32MP_DDR_BASE;
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priv->info.size = 0;
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return stm32mp1_ddr_setup();
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}
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