107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/*
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* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSEC2_REG_H
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#define BSEC2_REG_H
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#include <lib/utils_def.h>
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/* IP configuration */
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#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03
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#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */
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#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
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#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04
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#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */
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#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
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/* BSEC REGISTER OFFSET (base relative) */
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#define BSEC_OTP_CONF_OFF U(0x000)
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#define BSEC_OTP_CTRL_OFF U(0x004)
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#define BSEC_OTP_WRDATA_OFF U(0x008)
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#define BSEC_OTP_STATUS_OFF U(0x00C)
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#define BSEC_OTP_LOCK_OFF U(0x010)
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#define BSEC_DEN_OFF U(0x014)
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#define BSEC_DISTURBED_OFF U(0x01C)
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#define BSEC_DISTURBED1_OFF U(0x020)
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#define BSEC_DISTURBED2_OFF U(0x024)
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#define BSEC_ERROR_OFF U(0x034)
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#define BSEC_ERROR1_OFF U(0x038)
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#define BSEC_ERROR2_OFF U(0x03C)
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#define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */
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#define BSEC_WRLOCK1_OFF U(0x050)
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#define BSEC_WRLOCK2_OFF U(0x054)
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#define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */
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#define BSEC_SPLOCK1_OFF U(0x068)
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#define BSEC_SPLOCK2_OFF U(0x06C)
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#define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */
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#define BSEC_SWLOCK1_OFF U(0x080)
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#define BSEC_SWLOCK2_OFF U(0x084)
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#define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */
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#define BSEC_SRLOCK1_OFF U(0x098)
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#define BSEC_SRLOCK2_OFF U(0x09C)
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#define BSEC_JTAG_IN_OFF U(0x0AC)
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#define BSEC_JTAG_OUT_OFF U(0x0B0)
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#define BSEC_SCRATCH_OFF U(0x0B4)
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#define BSEC_OTP_DATA_OFF U(0x200)
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#define BSEC_IPHW_CFG_OFF U(0xFF0)
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#define BSEC_IPVR_OFF U(0xFF4)
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#define BSEC_IP_ID_OFF U(0xFF8)
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#define BSEC_IP_MAGIC_ID_OFF U(0xFFC)
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#define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n))
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#define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n))
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#define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n))
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#define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n))
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/* BSEC_CONFIGURATION Register */
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#define BSEC_CONF_POWER_UP_MASK BIT(0)
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#define BSEC_CONF_POWER_UP_SHIFT 0
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#define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
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#define BSEC_CONF_FRQ_SHIFT 1
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#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
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#define BSEC_CONF_PRG_WIDTH_SHIFT 3
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#define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
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#define BSEC_CONF_TREAD_SHIFT 7
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/* BSEC_CONTROL Register */
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#define BSEC_READ 0U
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#define BSEC_WRITE BIT(8)
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#define BSEC_LOCK BIT(9)
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/* BSEC_OTP_LOCK register */
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#define UPPER_OTP_LOCK_MASK BIT(0)
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#define UPPER_OTP_LOCK_SHIFT 0
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#define DENREG_LOCK_MASK BIT(2)
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#define DENREG_LOCK_SHIFT 2
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#define GPLOCK_LOCK_MASK BIT(4)
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#define GPLOCK_LOCK_SHIFT 4
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/* BSEC_OTP_STATUS Register */
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#define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
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#define BSEC_MODE_SECURE_MASK BIT(0)
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#define BSEC_MODE_FULLDBG_MASK BIT(1)
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#define BSEC_MODE_INVALID_MASK BIT(2)
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#define BSEC_MODE_BUSY_MASK BIT(3)
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#define BSEC_MODE_PROGFAIL_MASK BIT(4)
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#define BSEC_MODE_PWR_MASK BIT(5)
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#define BSEC_MODE_BIST1_LOCK_MASK BIT(6)
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#define BSEC_MODE_BIST2_LOCK_MASK BIT(7)
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/* BSEC_DENABLE Register */
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#define BSEC_HDPEN BIT(4)
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#define BSEC_SPIDEN BIT(5)
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#define BSEC_SPINDEN BIT(6)
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#define BSEC_DBGSWGEN BIT(10)
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#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
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/* BSEC_FENABLE Register */
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#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
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/* BSEC_IPVR Register */
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#define BSEC_IPVR_MSK GENMASK(7, 0)
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#endif /* BSEC2_REG_H */
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