93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/*
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MORELLO_DEF_H
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#define MORELLO_DEF_H
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/* Non-secure SRAM MMU mapping */
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#define MORELLO_NS_SRAM_BASE UL(0x06000000)
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#define MORELLO_NS_SRAM_SIZE UL(0x00010000)
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#define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \
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MORELLO_NS_SRAM_BASE, \
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MORELLO_NS_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* SDS Platform information defines */
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#define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8)
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#define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0)
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#ifdef TARGET_PLATFORM_FVP
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# define MORELLO_SDS_PLATFORM_INFO_SIZE U(8)
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#else
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# define MORELLO_SDS_PLATFORM_INFO_SIZE U(22)
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#endif
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#define MORELLO_MAX_DDR_CAPACITY U(0x1000000000)
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#define MORELLO_MAX_REMOTE_CHIP_COUNT U(16)
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#define MORELLO_SCC_SERVER_MODE U(0)
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#define MORELLO_SCC_CLIENT_MODE_MASK U(1)
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#define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4)
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#define MORELLO_SCC_C2_TAG_CACHE_EN_MASK U(8)
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/* Base address of non-secure SRAM where Platform information will be filled */
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#define MORELLO_PLATFORM_INFO_BASE UL(0x06000000)
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/* DMC memory status registers */
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#define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000)
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#define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000)
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#define MORELLO_DMC_MEMC_STATUS_MASK U(7)
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/* DMC memory command registers */
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#define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008)
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#define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008)
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/* DMC capability control register */
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#define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00)
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#define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00)
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/* DMC tag cache control register */
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#define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04)
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#define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04)
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/* DMC tag cache config register */
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#define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08)
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#define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08)
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/* DMC memory access control register */
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#define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C)
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#define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C)
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#define MORELLO_DMC_MEM_ACCESS_DIS (1UL << 16)
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/* DMC memory address control register */
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#define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10)
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#define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10)
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/* DMC memory address control 2 register */
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#define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14)
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#define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14)
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/* DMC special control register */
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#define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18)
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#define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18)
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/* DMC ERR0CTLR0 registers */
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#define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708)
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#define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708)
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/* DMC ECC in ERR0CTLR0 register */
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#define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9)
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/* DMC ERR2STATUS register */
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#define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790)
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#define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790)
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/* DMC memory commands */
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#define MORELLO_DMC_MEMC_CMD_CONFIG U(0)
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#define MORELLO_DMC_MEMC_CMD_READY U(3)
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#endif /* MORELLO_DEF_H */
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