b5a0663771
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> |
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| .. | ||
| mss_common.mk | ||
| mss_ipc_drv.c | ||
| mss_ipc_drv.h | ||
| mss_mem.h | ||
| mss_scp_bl2_format.h | ||
| mss_scp_bootloader.c | ||
| mss_scp_bootloader.h | ||