550 lines
12 KiB
C
550 lines
12 KiB
C
/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/mmio.h>
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#include <mt_gic_v3.h>
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#include <mtk_cirq.h>
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static struct cirq_events cirq_all_events = {
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.spi_start = CIRQ_SPI_START,
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};
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static uint32_t already_cloned;
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/*
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* mt_irq_mask_restore: restore all interrupts
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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* (This is ONLY used for the idle current measurement by the factory mode.)
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*/
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int mt_irq_mask_restore(struct mtk_irq_mask *mask)
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{
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if (mask == NULL) {
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return -1;
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}
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if (mask->header != IRQ_MASK_HEADER) {
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return -1;
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}
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if (mask->footer != IRQ_MASK_FOOTER) {
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return -1;
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}
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4),
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mask->mask1);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8),
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mask->mask2);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc),
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mask->mask3);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10),
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mask->mask4);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14),
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mask->mask5);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18),
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mask->mask6);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c),
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mask->mask7);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20),
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mask->mask8);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24),
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mask->mask9);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28),
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mask->mask10);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x2c),
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mask->mask11);
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mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x30),
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mask->mask12);
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/* make sure dist changes happen */
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dsb();
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return 0;
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}
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/*
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* mt_irq_mask_all: disable all interrupts
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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* (This is ONLY used for the idle current measurement by the factory mode.)
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*/
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int mt_irq_mask_all(struct mtk_irq_mask *mask)
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{
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if (mask != NULL) {
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/* for SPI */
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mask->mask1 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x4));
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mask->mask2 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x8));
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mask->mask3 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0xc));
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mask->mask4 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x10));
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mask->mask5 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x14));
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mask->mask6 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x18));
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mask->mask7 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x1c));
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mask->mask8 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x20));
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mask->mask9 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x24));
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mask->mask10 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x28));
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mask->mask11 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x2c));
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mask->mask12 = mmio_read_32((BASE_GICD_BASE +
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GICD_ISENABLER + 0x30));
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/* for SPI */
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x4),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x8),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0xC),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x10),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x14),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x18),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x1C),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x20),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x24),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x28),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x2c),
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0xFFFFFFFF);
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mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x30),
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0xFFFFFFFF);
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/* make sure distributor changes happen */
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dsb();
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mask->header = IRQ_MASK_HEADER;
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mask->footer = IRQ_MASK_FOOTER;
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return 0;
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} else {
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return -1;
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}
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}
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static uint32_t mt_irq_get_pol(uint32_t irq)
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{
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#ifdef CIRQ_WITH_POLARITY
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uint32_t reg;
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uint32_t base = INT_POL_CTL0;
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if (irq < 32U) {
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return 0;
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}
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reg = ((irq - 32U) / 32U);
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return mmio_read_32(base + reg * 4U);
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#else
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return 0;
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#endif
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}
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unsigned int mt_irq_get_sens(unsigned int irq)
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{
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unsigned int config;
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/*
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* 2'b10 edge
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* 2'b01 level
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*/
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config = mmio_read_32(MT_GIC_BASE + GICD_ICFGR + (irq / 16U) * 4U);
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config = (config >> (irq % 16U) * 2U) & 0x3;
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return config;
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}
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static void collect_all_wakeup_events(void)
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{
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unsigned int i;
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uint32_t gic_irq;
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uint32_t cirq;
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uint32_t cirq_reg;
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uint32_t cirq_offset;
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uint32_t mask;
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uint32_t pol_mask;
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uint32_t irq_offset;
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uint32_t irq_mask;
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if ((cirq_all_events.wakeup_events == NULL) ||
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cirq_all_events.num_of_events == 0U) {
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return;
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}
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for (i = 0U; i < cirq_all_events.num_of_events; i++) {
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if (cirq_all_events.wakeup_events[i] > 0U) {
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gic_irq = cirq_all_events.wakeup_events[i];
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cirq = gic_irq - cirq_all_events.spi_start - 32U;
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cirq_reg = cirq / 32U;
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cirq_offset = cirq % 32U;
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mask = 0x1 << cirq_offset;
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irq_offset = gic_irq % 32U;
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irq_mask = 0x1 << irq_offset;
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/*
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* CIRQ default masks all
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*/
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cirq_all_events.table[cirq_reg].mask |= mask;
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/*
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* CIRQ default pol is low
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*/
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pol_mask = mt_irq_get_pol(
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cirq_all_events.wakeup_events[i])
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& irq_mask;
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/*
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* 0 means rising
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*/
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if (pol_mask == 0U) {
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cirq_all_events.table[cirq_reg].pol |= mask;
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}
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/*
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* CIRQ could monitor edge/level trigger
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* cirq register (0: edge, 1: level)
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*/
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if (mt_irq_get_sens(cirq_all_events.wakeup_events[i])
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== SENS_EDGE) {
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cirq_all_events.table[cirq_reg].sen |= mask;
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}
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cirq_all_events.table[cirq_reg].used = 1U;
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cirq_all_events.table[cirq_reg].reg_num = cirq_reg;
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}
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}
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}
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/*
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* mt_cirq_set_pol: Set the polarity for the specified SYS_CIRQ number.
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* @cirq_num: the SYS_CIRQ number to set
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* @pol: polarity to set
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* @return:
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* 0: set pol success
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* -1: cirq num is out of range
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*/
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#ifdef CIRQ_WITH_POLARITY
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static int mt_cirq_set_pol(uint32_t cirq_num, uint32_t pol)
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{
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uint32_t base;
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uint32_t bit = 1U << (cirq_num % 32U);
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if (cirq_num >= CIRQ_IRQ_NUM) {
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return -1;
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}
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if (pol == MT_CIRQ_POL_NEG) {
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base = (cirq_num / 32U) * 4U + CIRQ_POL_CLR_BASE;
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} else if (pol == MT_CIRQ_POL_POS) {
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base = (cirq_num / 32U) * 4U + CIRQ_POL_SET_BASE;
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} else {
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return -1;
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}
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mmio_write_32(base, bit);
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return 0;
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}
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#endif
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/*
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* mt_cirq_mask: Mask the specified SYS_CIRQ.
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* @cirq_num: the SYS_CIRQ number to mask
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* @return:
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* 0: mask success
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* -1: cirq num is out of range
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*/
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static int mt_cirq_mask(uint32_t cirq_num)
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{
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uint32_t bit = 1U << (cirq_num % 32U);
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if (cirq_num >= CIRQ_IRQ_NUM) {
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return -1;
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}
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mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE, bit);
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return 0;
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}
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/*
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* mt_cirq_unmask: Unmask the specified SYS_CIRQ.
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* @cirq_num: the SYS_CIRQ number to unmask
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* @return:
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* 0: umask success
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* -1: cirq num is out of range
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*/
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static int mt_cirq_unmask(uint32_t cirq_num)
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{
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uint32_t bit = 1U << (cirq_num % 32U);
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if (cirq_num >= CIRQ_IRQ_NUM) {
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return -1;
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}
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mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE, bit);
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return 0;
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}
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uint32_t mt_irq_get_en(uint32_t irq)
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{
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uint32_t addr, st, val;
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addr = BASE_GICD_BASE + GICD_ISENABLER + (irq / 32U) * 4U;
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st = mmio_read_32(addr);
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val = (st >> (irq % 32U)) & 1U;
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return val;
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}
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static void __cirq_fast_clone(void)
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{
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struct cirq_reg *reg;
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unsigned int i;
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for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
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uint32_t cirq_bit;
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reg = &cirq_all_events.table[i];
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if (reg->used == 0U) {
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continue;
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}
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mmio_write_32(CIRQ_SENS_CLR_BASE + (reg->reg_num * 4U),
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reg->sen);
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for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
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uint32_t val, cirq_id;
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uint32_t gic_id;
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#ifdef CIRQ_WITH_POLARITY
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uint32_t gic_bit, pol;
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#endif
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uint32_t en;
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val = ((1U << cirq_bit) & reg->mask);
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if (val == 0U) {
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continue;
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}
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cirq_id = (reg->reg_num << 5U) + cirq_bit;
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gic_id = CIRQ_TO_IRQ_NUM(cirq_id);
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#ifdef CIRQ_WITH_POLARITY
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gic_bit = (0x1U << ((gic_id - 32U) % 32U));
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pol = mt_irq_get_pol(gic_id) & gic_bit;
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if (pol != 0U) {
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mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_NEG);
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} else {
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mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_POS);
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}
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#endif
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en = mt_irq_get_en(gic_id);
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if (en == 1U) {
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mt_cirq_unmask(cirq_id);
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} else {
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mt_cirq_mask(cirq_id);
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}
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}
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}
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}
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static void cirq_fast_clone(void)
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{
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if (already_cloned == 0U) {
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collect_all_wakeup_events();
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already_cloned = 1U;
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}
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__cirq_fast_clone();
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}
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void set_wakeup_sources(uint32_t *list, uint32_t num_of_events)
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{
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cirq_all_events.num_of_events = num_of_events;
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cirq_all_events.wakeup_events = list;
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}
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/*
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* mt_cirq_clone_gic: Copy the setting from GIC to SYS_CIRQ
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*/
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void mt_cirq_clone_gic(void)
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{
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cirq_fast_clone();
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}
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uint32_t mt_irq_get_pending_vec(uint32_t start_irq)
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{
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uint32_t base = 0U;
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uint32_t pending_vec = 0U;
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uint32_t reg = start_irq / 32U;
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uint32_t LSB_num, MSB_num;
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uint32_t LSB_vec, MSB_vec;
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base = BASE_GICD_BASE;
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/* if start_irq is not aligned 32, do some assembling */
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MSB_num = start_irq % 32U;
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if (MSB_num != 0U) {
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LSB_num = 32U - MSB_num;
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LSB_vec = mmio_read_32(base + GICD_ISPENDR +
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reg * 4U) >> MSB_num;
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MSB_vec = mmio_read_32(base + GICD_ISPENDR +
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(reg + 1U) * 4U) << LSB_num;
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pending_vec = MSB_vec | LSB_vec;
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} else {
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pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4);
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}
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return pending_vec;
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}
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static int mt_cirq_get_mask_vec(unsigned int i)
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{
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return mmio_read_32((i * 4U) + CIRQ_MASK_BASE);
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}
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/*
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* mt_cirq_ack_all: Ack all the interrupt on SYS_CIRQ
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*/
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void mt_cirq_ack_all(void)
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{
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uint32_t ack_vec, pend_vec, mask_vec;
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unsigned int i;
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for (i = 0; i < CIRQ_CTRL_REG_NUM; i++) {
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/*
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* if a irq is pending & not masked, don't ack it
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* , since cirq start irq might not be 32 aligned with gic,
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* need an exotic API to get proper vector of pending irq
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*/
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pend_vec = mt_irq_get_pending_vec(CIRQ_SPI_START
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+ (i + 1U) * 32U);
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mask_vec = mt_cirq_get_mask_vec(i);
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/* those should be acked are: "not (pending & not masked)",
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*/
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ack_vec = (~pend_vec) | mask_vec;
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mmio_write_32(CIRQ_ACK_BASE + (i * 4U), ack_vec);
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}
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/*
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* make sure all cirq setting take effect
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* before doing other things
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*/
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dsb();
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}
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/*
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* mt_cirq_enable: Enable SYS_CIRQ
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*/
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void mt_cirq_enable(void)
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{
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uint32_t st;
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/* level only */
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mt_cirq_ack_all();
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st = mmio_read_32(CIRQ_CON);
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/*
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* CIRQ could monitor edge/level trigger
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*/
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st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS);
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mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
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}
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/*
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* mt_cirq_disable: Disable SYS_CIRQ
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*/
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void mt_cirq_disable(void)
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{
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uint32_t st;
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st = mmio_read_32(CIRQ_CON);
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st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS);
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mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
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}
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void mt_irq_unmask_for_sleep_ex(uint32_t irq)
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{
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uint32_t mask;
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mask = 1U << (irq % 32U);
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mmio_write_32(BASE_GICD_BASE + GICD_ISENABLER +
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((irq / 32U) * 4U), mask);
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}
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void mt_cirq_mask_all(void)
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{
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unsigned int i;
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for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
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mmio_write_32(CIRQ_MASK_SET_BASE + (i * 4U), 0xFFFFFFFF);
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}
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dsb();
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}
|
|
|
|
static void cirq_fast_sw_flush(void)
|
|
{
|
|
struct cirq_reg *reg;
|
|
unsigned int i;
|
|
|
|
for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
|
|
uint32_t cirq_bit;
|
|
|
|
reg = &cirq_all_events.table[i];
|
|
|
|
if (reg->used == 0U) {
|
|
continue;
|
|
}
|
|
|
|
reg->pending = mmio_read_32(CIRQ_STA_BASE +
|
|
(reg->reg_num << 2U));
|
|
reg->pending &= reg->mask;
|
|
|
|
for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
|
|
uint32_t val, cirq_id;
|
|
|
|
val = (1U << cirq_bit) & reg->pending;
|
|
if (val == 0U) {
|
|
continue;
|
|
}
|
|
|
|
cirq_id = (reg->reg_num << 5U) + cirq_bit;
|
|
mt_irq_set_pending(CIRQ_TO_IRQ_NUM(cirq_id));
|
|
if (CIRQ_TO_IRQ_NUM(cirq_id) == MD_WDT_IRQ_BIT_ID) {
|
|
INFO("Set MD_WDT_IRQ pending in %s\n",
|
|
__func__);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* mt_cirq_disable: Flush interrupt from SYS_CIRQ to GIC
|
|
*/
|
|
void mt_cirq_flush(void)
|
|
{
|
|
cirq_fast_sw_flush();
|
|
mt_cirq_mask_all();
|
|
mt_cirq_ack_all();
|
|
}
|
|
|
|
void mt_cirq_sw_reset(void)
|
|
{
|
|
uint32_t st;
|
|
|
|
st = mmio_read_32(CIRQ_CON);
|
|
st |= (CIRQ_SW_RESET << CIRQ_CON_SW_RST_BITS);
|
|
mmio_write_32(CIRQ_CON, st);
|
|
}
|