256 lines
8.3 KiB
C
256 lines
8.3 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#endif /* __ASSEMBLER__ */
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#include <platform_def.h>
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#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
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#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
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#define MP2_CPUCFG MCUCFG_REG(0x2208)
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#define MP2_CPU0_STANDBYWFE BIT(4)
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#define MP2_CPU1_STANDBYWFE BIT(5)
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#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
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#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
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#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
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#define sw_spark_en BIT(0)
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#define sw_no_wait_for_q_channel BIT(1)
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#define sw_fsm_override BIT(2)
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#define sw_logic_pre1_pdb BIT(3)
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#define sw_logic_pre2_pdb BIT(4)
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#define sw_logic_pdb BIT(5)
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#define sw_iso BIT(6)
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#define sw_sram_sleepb (U(0x3F) << 7)
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#define sw_sram_isointb BIT(13)
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#define sw_clk_dis BIT(14)
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#define sw_ckiso BIT(15)
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#define sw_pd (U(0x3F) << 16)
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#define sw_hot_plug_reset BIT(22)
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#define sw_pwr_on_override_en BIT(23)
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#define sw_pwr_on BIT(24)
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#define sw_coq_dis BIT(25)
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#define logic_pdbo_all_off_ack BIT(26)
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#define logic_pdbo_all_on_ack BIT(27)
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#define logic_pre2_pdbo_all_on_ack BIT(28)
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#define logic_pre1_pdbo_all_on_ack BIT(29)
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#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
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(MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
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#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
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#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
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#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
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#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
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#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
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#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
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#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
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#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
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#define cpu_sw_spark_en BIT(0)
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#define cpu_sw_no_wait_for_q_channel BIT(1)
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#define cpu_sw_fsm_override BIT(2)
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#define cpu_sw_logic_pre1_pdb BIT(3)
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#define cpu_sw_logic_pre2_pdb BIT(4)
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#define cpu_sw_logic_pdb BIT(5)
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#define cpu_sw_iso BIT(6)
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#define cpu_sw_sram_sleepb BIT(7)
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#define cpu_sw_sram_isointb BIT(8)
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#define cpu_sw_clk_dis BIT(9)
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#define cpu_sw_ckiso BIT(10)
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#define cpu_sw_pd (U(0x1F) << 11)
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#define cpu_sw_hot_plug_reset BIT(16)
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#define cpu_sw_powr_on_override_en BIT(17)
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#define cpu_sw_pwr_on BIT(18)
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#define cpu_spark2ldo_allswoff BIT(19)
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#define cpu_pdbo_all_on_ack BIT(20)
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#define cpu_pre2_pdbo_allon_ack BIT(21)
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#define cpu_pre1_pdbo_allon_ack BIT(22)
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/* CPC related registers */
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#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
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#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
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#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
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#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
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#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
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#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
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#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
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#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
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#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
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#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
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#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
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#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
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#define SPARK2LDO MCUCFG_REG(0x2700)
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/* APB module mcucfg */
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#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
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#define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
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#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
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#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
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#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
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#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8))
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#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
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#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
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#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
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#define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
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#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
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#define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
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#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
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#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
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#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
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#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8))
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#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
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#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
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#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
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#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
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#define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
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#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
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#define MP0_SPMC MCUCFG_REG(0x788)
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#define MP1_SPMC MCUCFG_REG(0x78C)
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#define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
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#define MP2_AXI_CONFIG_ACINACTM BIT(0)
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#define MP2_AXI_CONFIG_AINACTS BIT(4)
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#define MPx_AXI_CONFIG_ACINACTM BIT(4)
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#define MPx_AXI_CONFIG_AINACTS BIT(5)
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#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
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#define MP0_CPU0_STANDBYWFE BIT(20)
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#define MP0_CPU1_STANDBYWFE BIT(21)
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#define MP0_CPU2_STANDBYWFE BIT(22)
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#define MP0_CPU3_STANDBYWFE BIT(23)
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#define MP1_CPU0_STANDBYWFE BIT(20)
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#define MP1_CPU1_STANDBYWFE BIT(21)
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#define MP1_CPU2_STANDBYWFE BIT(22)
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#define MP1_CPU3_STANDBYWFE BIT(23)
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#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
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#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
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#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
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#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
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#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
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#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
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#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
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#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
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#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
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#define MP2_COQ MCUCFG_REG(0x22BC)
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#define MP2_COQ_SW_DIS BIT(0)
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#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
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#define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
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#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
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#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
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#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
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#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
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#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
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#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
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#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)
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#define MP2_SW_RST_B BIT(0)
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#define MP2_TOPAON_APB_MASK BIT(1)
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#define B_SW_HOT_PLUG_RESET BIT(30)
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#define B_SW_PD_OFFSET (18U)
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#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET)
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#define B_SW_SRAM_SLEEPB_OFFSET (12U)
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#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
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#define B_SW_SRAM_ISOINTB BIT(9)
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#define B_SW_ISO BIT(8)
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#define B_SW_LOGIC_PDB BIT(7)
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#define B_SW_LOGIC_PRE2_PDB BIT(6)
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#define B_SW_LOGIC_PRE1_PDB BIT(5)
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#define B_SW_FSM_OVERRIDE BIT(4)
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#define B_SW_PWR_ON BIT(3)
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#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
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#define B_FSM_STATE_OUT_OFFSET (6U)
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#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET)
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#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
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#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
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#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
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#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
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#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET)
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#ifndef __ASSEMBLER__
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/* cpu boot mode */
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enum {
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MP0_CPUCFG_64BIT_SHIFT = 12U,
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MP1_CPUCFG_64BIT_SHIFT = 28U,
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MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
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MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4U,
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MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12U,
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MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14U,
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MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
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};
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#endif /* __ASSEMBLER__ */
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#endif /* MCUCFG_H */
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