476 lines
11 KiB
C
476 lines
11 KiB
C
/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include <plat_gic.h>
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#include <plat_common.h>
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#include <plat_psci.h>
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#ifdef NXP_WARM_BOOT
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#include <plat_warm_rst.h>
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#endif
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#include <platform_def.h>
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#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
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static void __dead2 _no_return_wfi(void)
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{
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_bl31_dead_wfi:
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wfi();
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goto _bl31_dead_wfi;
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}
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#endif
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#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
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/* the entry for core warm boot */
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static uintptr_t warmboot_entry = (uintptr_t) NULL;
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#endif
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#if (SOC_CORE_RELEASE)
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static int _pwr_domain_on(u_register_t mpidr)
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{
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int core_pos = plat_core_pos(mpidr);
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int rc = PSCI_E_INVALID_PARAMS;
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u_register_t core_mask;
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if (core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT) {
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_soc_set_start_addr(warmboot_entry);
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dsb();
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isb();
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core_mask = (1 << core_pos);
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rc = _psci_cpu_on(core_mask);
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}
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return (rc);
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}
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#endif
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#if (SOC_CORE_OFF)
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static void _pwr_domain_off(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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/* set core state in internal data */
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core_state = CORE_OFF_PENDING;
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_setCoreState(core_mask, core_state);
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_psci_cpu_prep_off(core_mask);
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}
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#endif
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#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
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static void __dead2 _pwr_down_wfi(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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switch (core_state) {
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#if (SOC_CORE_OFF)
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case CORE_OFF_PENDING:
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/* set core state in internal data */
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core_state = CORE_OFF;
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_setCoreState(core_mask, core_state);
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/* turn the core off */
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_psci_cpu_off_wfi(core_mask, warmboot_entry);
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break;
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#endif
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#if (SOC_CORE_PWR_DWN)
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case CORE_PWR_DOWN:
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/* power-down the core */
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_psci_cpu_pwrdn_wfi(core_mask, warmboot_entry);
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break;
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#endif
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#if (SOC_SYSTEM_PWR_DWN)
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case SYS_OFF_PENDING:
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/* set core state in internal data */
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core_state = SYS_OFF;
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_setCoreState(core_mask, core_state);
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/* power-down the system */
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_psci_sys_pwrdn_wfi(core_mask, warmboot_entry);
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break;
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#endif
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default:
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_no_return_wfi();
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break;
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}
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}
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#endif
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#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
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static void _pwr_domain_wakeup(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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switch (core_state) {
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case CORE_PENDING: /* this core is coming out of reset */
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/* soc per cpu setup */
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soc_init_percpu();
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/* gic per cpu setup */
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plat_gic_pcpu_init();
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/* set core state in internal data */
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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break;
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#if (SOC_CORE_RESTART)
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case CORE_WAKEUP:
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/* this core is waking up from OFF */
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_psci_wakeup(core_mask);
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/* set core state in internal data */
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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break;
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#endif
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}
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}
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#endif
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#if (SOC_CORE_STANDBY)
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static void _pwr_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (cpu_state == PLAT_MAX_RET_STATE) {
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/* set core state to standby */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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_psci_core_entr_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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}
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}
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#endif
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#if (SOC_CORE_PWR_DWN)
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static void _pwr_suspend(const psci_power_state_t *state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_SYSTEM_PWR_DWN)
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_psci_sys_prep_pwrdn(core_mask);
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/* set core state */
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core_state = SYS_OFF_PENDING;
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_setCoreState(core_mask, core_state);
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#endif
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} else if (state->pwr_domain_state[PLAT_MAX_LVL]
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== PLAT_MAX_RET_STATE) {
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#if (SOC_SYSTEM_STANDBY)
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_psci_sys_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_OFF_STATE) {
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#if (SOC_CLUSTER_PWR_DWN)
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_psci_clstr_prep_pwrdn(core_mask);
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/* set core state */
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core_state = CORE_PWR_DOWN;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_RET_STATE) {
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#if (SOC_CLUSTER_STANDBY)
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_psci_clstr_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_CORE_PWR_DWN)
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/* prep the core for power-down */
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_psci_core_prep_pwrdn(core_mask);
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/* set core state */
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core_state = CORE_PWR_DOWN;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
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#if (SOC_CORE_STANDBY)
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_psci_core_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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}
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#endif
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#if (SOC_CORE_PWR_DWN)
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static void _pwr_suspend_finish(const psci_power_state_t *state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_SYSTEM_PWR_DWN)
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_psci_sys_exit_pwrdn(core_mask);
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/* when we are here, the core is back up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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} else if (state->pwr_domain_state[PLAT_MAX_LVL]
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== PLAT_MAX_RET_STATE) {
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#if (SOC_SYSTEM_STANDBY)
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_psci_sys_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_OFF_STATE) {
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#if (SOC_CLUSTER_PWR_DWN)
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_psci_clstr_exit_pwrdn(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_RET_STATE) {
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#if (SOC_CLUSTER_STANDBY)
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_psci_clstr_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_CORE_PWR_DWN)
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_psci_core_exit_pwrdn(core_mask);
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/* when we are here, the core is back up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
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#if (SOC_CORE_STANDBY)
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_psci_core_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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}
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#endif
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#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
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#define PWR_STATE_TYPE_MASK 0x00010000
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#define PWR_STATE_TYPE_STNDBY 0x0
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#define PWR_STATE_TYPE_PWRDWN 0x00010000
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#define PWR_STATE_LVL_MASK 0x03000000
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#define PWR_STATE_LVL_CORE 0x0
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#define PWR_STATE_LVL_CLSTR 0x01000000
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#define PWR_STATE_LVL_SYS 0x02000000
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#define PWR_STATE_LVL_MAX 0x03000000
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/* turns a requested power state into a target power state
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* based on SoC capabilities
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*/
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static int _pwr_state_validate(uint32_t pwr_state,
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psci_power_state_t *state)
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{
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int stat = PSCI_E_INVALID_PARAMS;
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int pwrdn = (pwr_state & PWR_STATE_TYPE_MASK);
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int lvl = (pwr_state & PWR_STATE_LVL_MASK);
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switch (lvl) {
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case PWR_STATE_LVL_MAX:
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if (pwrdn && SOC_SYSTEM_PWR_DWN)
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state->pwr_domain_state[PLAT_MAX_LVL] =
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PLAT_MAX_OFF_STATE;
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else if (SOC_SYSTEM_STANDBY)
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state->pwr_domain_state[PLAT_MAX_LVL] =
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PLAT_MAX_RET_STATE;
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/* intentional fall-thru condition */
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case PWR_STATE_LVL_SYS:
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if (pwrdn && SOC_SYSTEM_PWR_DWN)
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state->pwr_domain_state[PLAT_SYS_LVL] =
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PLAT_MAX_OFF_STATE;
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else if (SOC_SYSTEM_STANDBY)
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state->pwr_domain_state[PLAT_SYS_LVL] =
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PLAT_MAX_RET_STATE;
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/* intentional fall-thru condition */
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case PWR_STATE_LVL_CLSTR:
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if (pwrdn && SOC_CLUSTER_PWR_DWN)
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state->pwr_domain_state[PLAT_CLSTR_LVL] =
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PLAT_MAX_OFF_STATE;
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else if (SOC_CLUSTER_STANDBY)
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state->pwr_domain_state[PLAT_CLSTR_LVL] =
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PLAT_MAX_RET_STATE;
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/* intentional fall-thru condition */
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case PWR_STATE_LVL_CORE:
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stat = PSCI_E_SUCCESS;
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if (pwrdn && SOC_CORE_PWR_DWN)
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state->pwr_domain_state[PLAT_CORE_LVL] =
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PLAT_MAX_OFF_STATE;
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else if (SOC_CORE_STANDBY)
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state->pwr_domain_state[PLAT_CORE_LVL] =
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PLAT_MAX_RET_STATE;
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break;
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}
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return (stat);
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}
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#endif
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#if (SOC_SYSTEM_PWR_DWN)
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static void _pwr_state_sys_suspend(psci_power_state_t *req_state)
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{
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/* if we need to have per-SoC settings, then we need to
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* extend this by calling into psci_utils.S and from there
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* on down to the SoC.S files
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*/
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req_state->pwr_domain_state[PLAT_MAX_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_SYS_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_CLSTR_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_CORE_LVL] = PLAT_MAX_OFF_STATE;
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}
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#endif
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#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
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static int psci_system_reset2(int is_vendor,
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int reset_type,
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u_register_t cookie)
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{
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int ret = 0;
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INFO("Executing the sequence of warm reset.\n");
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ret = prep_n_execute_warm_reset();
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return ret;
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}
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#endif
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static plat_psci_ops_t _psci_pm_ops = {
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#if (SOC_SYSTEM_OFF)
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.system_off = _psci_system_off,
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#endif
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#if (SOC_SYSTEM_RESET)
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.system_reset = _psci_system_reset,
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#endif
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#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
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.system_reset2 = psci_system_reset2,
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#endif
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#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
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/* core released or restarted */
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.pwr_domain_on_finish = _pwr_domain_wakeup,
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#endif
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#if (SOC_CORE_OFF)
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/* core shutting down */
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.pwr_domain_off = _pwr_domain_off,
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#endif
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#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
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.pwr_domain_pwr_down_wfi = _pwr_down_wfi,
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#endif
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#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
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/* cpu_suspend */
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.validate_power_state = _pwr_state_validate,
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#if (SOC_CORE_STANDBY)
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.cpu_standby = _pwr_cpu_standby,
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#endif
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#if (SOC_CORE_PWR_DWN)
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.pwr_domain_suspend = _pwr_suspend,
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.pwr_domain_suspend_finish = _pwr_suspend_finish,
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#endif
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#endif
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#if (SOC_SYSTEM_PWR_DWN)
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.get_sys_suspend_power_state = _pwr_state_sys_suspend,
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#endif
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#if (SOC_CORE_RELEASE)
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/* core executing psci_cpu_on */
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.pwr_domain_on = _pwr_domain_on
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#endif
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};
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#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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warmboot_entry = sec_entrypoint;
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*psci_ops = &_psci_pm_ops;
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return 0;
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}
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#else
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &_psci_pm_ops;
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return 0;
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}
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#endif
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