275 lines
7.3 KiB
Makefile
275 lines
7.3 KiB
Makefile
#
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# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/renesas/common/common.mk
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ifndef LSI
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$(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI")
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else
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ifeq (${LSI},AUTO)
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RCAR_LSI:=${RCAR_AUTO}
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else ifeq (${LSI},G2M)
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RCAR_LSI:=${RZ_G2M}
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ifndef LSI_CUT
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# enable compatible function.
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RCAR_LSI_CUT_COMPAT := 1
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$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
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else
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# disable compatible function.
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ifeq (${LSI_CUT},10)
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RCAR_LSI_CUT:=0
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else ifeq (${LSI_CUT},11)
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RCAR_LSI_CUT:=1
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else ifeq (${LSI_CUT},13)
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RCAR_LSI_CUT:=3
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else ifeq (${LSI_CUT},30)
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RCAR_LSI_CUT:=20
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else
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$(error "Error: ${LSI_CUT} is not supported.")
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endif
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$(eval $(call add_define,RCAR_LSI_CUT))
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endif
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else ifeq (${LSI},G2H)
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RCAR_LSI:=${RZ_G2H}
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ifndef LSI_CUT
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# enable compatible function.
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RCAR_LSI_CUT_COMPAT := 1
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$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
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else
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# disable compatible function.
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ifeq (${LSI_CUT},30)
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RCAR_LSI_CUT:=20
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else
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$(error "Error: ${LSI_CUT} is not supported.")
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endif
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$(eval $(call add_define,RCAR_LSI_CUT))
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endif
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else ifeq (${LSI},G2N)
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RCAR_LSI:=${RZ_G2N}
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ifndef LSI_CUT
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# enable compatible function.
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RCAR_LSI_CUT_COMPAT := 1
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$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
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else
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# disable compatible function.
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ifeq (${LSI_CUT},10)
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RCAR_LSI_CUT:=0
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else ifeq (${LSI_CUT},11)
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RCAR_LSI_CUT:=1
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else
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$(error "Error: ${LSI_CUT} is not supported.")
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endif
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$(eval $(call add_define,RCAR_LSI_CUT))
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endif
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else ifeq (${LSI},G2E)
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RCAR_LSI:=${RZ_G2E}
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ifndef LSI_CUT
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# enable compatible function.
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RCAR_LSI_CUT_COMPAT := 1
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$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
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else
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# disable compatible function.
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ifeq (${LSI_CUT},10)
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RCAR_LSI_CUT:=0
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else ifeq (${LSI_CUT},11)
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RCAR_LSI_CUT:=1
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else
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$(error "Error: ${LSI_CUT} is not supported.")
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endif
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$(eval $(call add_define,RCAR_LSI_CUT))
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endif
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else
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$(error "Error: ${LSI} is not supported.")
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endif
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$(eval $(call add_define,RCAR_LSI))
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endif
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# Process RZG_LCS_STATE_DETECTION_ENABLE flag
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# Enable to get LCS state information
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ifndef RZG_LCS_STATE_DETECTION_ENABLE
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RZG_LCS_STATE_DETECTION_ENABLE := 0
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endif
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$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE))
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# Process RCAR_SECURE_BOOT flag
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ifndef RCAR_SECURE_BOOT
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RCAR_SECURE_BOOT := 0
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endif
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$(eval $(call add_define,RCAR_SECURE_BOOT))
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# LCS state of RZ/G2 Chip is all CM.
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# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings
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# which results in getting incorrect LCS states
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# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings.
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ifeq (${RCAR_SECURE_BOOT},1)
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ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0)
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$(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.")
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endif
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endif
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# lock RPC HYPERFLASH access by default
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# unlock to repogram the ATF firmware from u-boot
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ifndef RCAR_RPC_HYPERFLASH_LOCKED
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RCAR_RPC_HYPERFLASH_LOCKED := 1
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endif
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$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED))
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# Process RCAR_QOS_TYPE flag
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ifndef RCAR_QOS_TYPE
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RCAR_QOS_TYPE := 0
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endif
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$(eval $(call add_define,RCAR_QOS_TYPE))
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# Process RCAR_DRAM_SPLIT flag
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ifndef RCAR_DRAM_SPLIT
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RCAR_DRAM_SPLIT := 0
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endif
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$(eval $(call add_define,RCAR_DRAM_SPLIT))
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# Process RCAR_BL33_EXECUTION_EL flag
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ifndef RCAR_BL33_EXECUTION_EL
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RCAR_BL33_EXECUTION_EL := 0
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endif
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$(eval $(call add_define,RCAR_BL33_EXECUTION_EL))
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# Process RCAR_AVS_SETTING_ENABLE flag
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ifndef AVS_SETTING_ENABLE
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AVS_SETTING_ENABLE := 0
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endif
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$(eval $(call add_define,AVS_SETTING_ENABLE))
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# Process RCAR_LOSSY_ENABLE flag
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ifndef RCAR_LOSSY_ENABLE
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RCAR_LOSSY_ENABLE := 0
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endif
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$(eval $(call add_define,RCAR_LOSSY_ENABLE))
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# Process LIFEC_DBSC_PROTECT_ENABLE flag
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ifndef LIFEC_DBSC_PROTECT_ENABLE
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LIFEC_DBSC_PROTECT_ENABLE := 1
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endif
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$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE))
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# Process RCAR_GEN3_ULCB flag
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ifndef RCAR_GEN3_ULCB
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RCAR_GEN3_ULCB := 0
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endif
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# Process RCAR_REF_INT flag
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ifndef RCAR_REF_INT
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RCAR_REF_INT :=0
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endif
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$(eval $(call add_define,RCAR_REF_INT))
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# Process RCAR_REWT_TRAINING flag
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ifndef RCAR_REWT_TRAINING
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RCAR_REWT_TRAINING := 1
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endif
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$(eval $(call add_define,RCAR_REWT_TRAINING))
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# Process RCAR_SYSTEM_SUSPEND flag
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ifndef RCAR_SYSTEM_SUSPEND
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RCAR_SYSTEM_SUSPEND := 0
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endif
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$(eval $(call add_define,RCAR_SYSTEM_SUSPEND))
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# Process RCAR_DRAM_LPDDR4_MEMCONF flag
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ifndef RCAR_DRAM_LPDDR4_MEMCONF
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RCAR_DRAM_LPDDR4_MEMCONF :=1
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endif
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$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
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# Process RCAR_DRAM_DDR3L_MEMCONF flag
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ifndef RCAR_DRAM_DDR3L_MEMCONF
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RCAR_DRAM_DDR3L_MEMCONF :=1
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endif
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$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF))
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# Process RCAR_DRAM_DDR3L_MEMDUAL flag
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ifndef RCAR_DRAM_DDR3L_MEMDUAL
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RCAR_DRAM_DDR3L_MEMDUAL :=1
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endif
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$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL))
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# Process RCAR_BL33_ARG0 flag
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ifdef RCAR_BL33_ARG0
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$(eval $(call add_define,RCAR_BL33_ARG0))
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endif
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#Process RCAR_BL2_DCACHE flag
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ifndef RCAR_BL2_DCACHE
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RCAR_BL2_DCACHE := 0
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endif
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$(eval $(call add_define,RCAR_BL2_DCACHE))
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# Process RCAR_DRAM_CHANNEL flag
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ifndef RCAR_DRAM_CHANNEL
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RCAR_DRAM_CHANNEL :=15
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endif
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$(eval $(call add_define,RCAR_DRAM_CHANNEL))
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#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag
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ifndef RCAR_SYSTEM_RESET_KEEPON_DDR
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RCAR_SYSTEM_RESET_KEEPON_DDR := 0
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endif
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$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
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RZG_SOC :=1
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$(eval $(call add_define,RZG_SOC))
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include drivers/renesas/common/ddr/ddr.mk
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include drivers/renesas/rzg/qos/qos.mk
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include drivers/renesas/rzg/pfc/pfc.mk
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include lib/libfdt/libfdt.mk
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PLAT_INCLUDES += -Idrivers/renesas/common/ddr \
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-Idrivers/renesas/rzg/qos \
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-Idrivers/renesas/rzg/board \
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-Idrivers/renesas/common \
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-Idrivers/renesas/common/iic_dvfs \
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-Idrivers/renesas/common/avs \
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-Idrivers/renesas/common/delay \
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-Idrivers/renesas/common/rom \
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-Idrivers/renesas/common/scif \
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-Idrivers/renesas/common/emmc \
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-Idrivers/renesas/common/pwrc \
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-Idrivers/renesas/common/io
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BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \
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drivers/renesas/rzg/board/board.c
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# build the layout images for the bootrom and the necessary srecords
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rzg: rzg_layout_create rzg_srecord
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distclean realclean clean: clean_layout_tool clean_srecord
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# layout images
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LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create
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clean_layout_tool:
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@echo "clean layout tool"
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${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean
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.PHONY: rzg_layout_create
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rzg_layout_create:
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@echo "generating layout srecs"
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${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
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# srecords
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SREC_PATH = ${BUILD_PLAT}
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BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf
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BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf
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clean_srecord:
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@echo "clean bl2 and bl31 srecs"
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rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
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.PHONY: rzg_srecord
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rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
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@echo "generating srec: ${SREC_PATH}/bl2.srec"
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$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec
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@echo "generating srec: ${SREC_PATH}/bl31.srec"
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$(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec
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