137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/arm/tzc400.h>
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#include <drivers/clk.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/soc/stm32mp15-tzc400.h>
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#include <lib/mmio.h>
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static unsigned int region_nb;
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static void init_tzc400_begin(unsigned int region0_attr)
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{
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tzc400_init(STM32MP1_TZC_BASE);
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tzc400_disable_filters();
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/* Region 0 set to cover all DRAM at 0xC000_0000 */
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tzc400_configure_region0(region0_attr, 0);
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region_nb = 1U;
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}
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static void init_tzc400_end(unsigned int action)
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{
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tzc400_set_action(action);
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tzc400_enable_filters();
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}
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static void tzc400_add_region(unsigned long long region_base,
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unsigned long long region_top, bool sec)
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{
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unsigned int sec_attr;
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unsigned int nsaid_permissions;
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if (sec) {
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sec_attr = TZC_REGION_S_RDWR;
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nsaid_permissions = 0;
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} else {
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sec_attr = TZC_REGION_S_NONE;
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nsaid_permissions = TZC_REGION_NSEC_ALL_ACCESS_RDWR;
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}
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tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, region_nb, region_base,
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region_top, sec_attr, nsaid_permissions);
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region_nb++;
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}
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/*******************************************************************************
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* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
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* and allow Non-Secure masters full access.
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******************************************************************************/
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static void init_tzc400(void)
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{
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unsigned long long region_base, region_top;
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unsigned long long ddr_base = STM32MP_DDR_BASE;
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unsigned long long ddr_ns_size =
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(unsigned long long)stm32mp_get_ddr_ns_size();
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unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
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unsigned long long ddr_top __unused;
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init_tzc400_begin(TZC_REGION_S_NONE);
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/*
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* Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
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* same configuration to all filters in the TZC.
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*/
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region_base = ddr_base;
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region_top = ddr_ns_top;
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tzc400_add_region(region_base, region_top, false);
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#ifdef AARCH32_SP_OPTEE
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/* Region 2 set to cover all secure DRAM. */
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region_base = region_top + 1U;
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region_top += STM32MP_DDR_S_SIZE;
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tzc400_add_region(region_base, region_top, true);
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ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U;
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if (region_top < ddr_top) {
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/* Region 3 set to cover non-secure memory DRAM after BL32. */
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region_base = region_top + 1U;
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region_top = ddr_top;
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tzc400_add_region(region_base, region_top, false);
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}
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#endif
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/*
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* Raise an interrupt (secure FIQ) if a NS device tries to access
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* secure memory
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*/
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init_tzc400_end(TZC_ACTION_INT);
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}
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/*******************************************************************************
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* Initialize the TrustZone Controller.
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* Early initialization create only one region with full access to secure.
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* This setting is used before and during DDR initialization.
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******************************************************************************/
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static void early_init_tzc400(void)
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{
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clk_enable(TZC1);
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clk_enable(TZC2);
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/* Region 0 set to cover all DRAM secure at 0xC000_0000 */
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init_tzc400_begin(TZC_REGION_S_RDWR);
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/* Raise an exception if a NS device tries to access secure memory */
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init_tzc400_end(TZC_ACTION_ERR);
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}
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/*******************************************************************************
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* Initialize the secure environment. At this moment only the TrustZone
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* Controller is initialized.
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******************************************************************************/
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void stm32mp1_arch_security_setup(void)
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{
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early_init_tzc400();
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}
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/*******************************************************************************
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* Initialize the secure environment. At this moment only the TrustZone
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* Controller is initialized.
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******************************************************************************/
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void stm32mp1_security_setup(void)
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{
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init_tzc400();
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}
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