406 lines
11 KiB
C
406 lines
11 KiB
C
/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef CLK_STM32_CORE_H
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#define CLK_STM32_CORE_H
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struct mux_cfg {
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uint16_t offset;
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uint8_t shift;
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uint8_t width;
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uint8_t bitrdy;
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};
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struct gate_cfg {
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uint16_t offset;
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uint8_t bit_idx;
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uint8_t set_clr;
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};
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struct clk_div_table {
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unsigned int val;
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unsigned int div;
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};
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struct div_cfg {
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uint16_t offset;
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uint8_t shift;
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uint8_t width;
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uint8_t flags;
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uint8_t bitrdy;
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const struct clk_div_table *table;
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};
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struct parent_cfg {
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uint8_t num_parents;
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const uint16_t *id_parents;
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struct mux_cfg *mux;
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};
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struct stm32_clk_priv;
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struct stm32_clk_ops {
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unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate);
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int (*get_parent)(struct stm32_clk_priv *priv, int id);
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int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate,
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unsigned long prate);
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int (*enable)(struct stm32_clk_priv *priv, int id);
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void (*disable)(struct stm32_clk_priv *priv, int id);
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bool (*is_enabled)(struct stm32_clk_priv *priv, int id);
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void (*init)(struct stm32_clk_priv *priv, int id);
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};
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struct clk_stm32 {
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const char *name;
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uint16_t binding;
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uint16_t parent;
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uint8_t flags;
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void *clock_cfg;
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const struct stm32_clk_ops *ops;
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};
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struct stm32_clk_priv {
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uintptr_t base;
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const uint32_t num;
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const struct clk_stm32 *clks;
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const struct parent_cfg *parents;
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const uint32_t nb_parents;
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const struct gate_cfg *gates;
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const uint32_t nb_gates;
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const struct div_cfg *div;
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const uint32_t nb_div;
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struct clk_oscillator_data *osci_data;
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const uint32_t nb_osci_data;
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uint32_t *gate_refcounts;
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void *pdata;
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};
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struct stm32_clk_bypass {
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uint16_t offset;
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uint8_t bit_byp;
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uint8_t bit_digbyp;
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};
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struct stm32_clk_css {
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uint16_t offset;
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uint8_t bit_css;
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};
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struct stm32_clk_drive {
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uint16_t offset;
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uint8_t drv_shift;
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uint8_t drv_width;
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uint8_t drv_default;
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};
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struct clk_oscillator_data {
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const char *name;
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uint16_t id_clk;
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unsigned long frequency;
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uint16_t gate_id;
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uint16_t gate_rdy_id;
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struct stm32_clk_bypass *bypass;
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struct stm32_clk_css *css;
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struct stm32_clk_drive *drive;
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};
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struct clk_fixed_rate {
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const char *name;
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unsigned long fixed_rate;
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};
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struct clk_gate_cfg {
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uint32_t offset;
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uint8_t bit_idx;
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};
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/* CLOCK FLAGS */
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#define CLK_IS_CRITICAL BIT(0)
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#define CLK_IGNORE_UNUSED BIT(1)
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#define CLK_SET_RATE_PARENT BIT(2)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
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#define CLK_DIVIDER_READ_ONLY BIT(5)
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
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#define MUX_MAX_PARENTS U(0x8000)
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#define MUX_PARENT_MASK GENMASK(14, 0)
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#define MUX_FLAG U(0x8000)
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#define MUX(mux) ((mux) | MUX_FLAG)
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#define NO_GATE 0
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#define _NO_ID UINT16_MAX
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#define CLK_IS_ROOT UINT16_MAX
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#define MUX_NO_BIT_RDY UINT8_MAX
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#define DIV_NO_BIT_RDY UINT8_MAX
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#define MASK_WIDTH_SHIFT(_width, _shift) \
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GENMASK(((_width) + (_shift) - 1U), (_shift))
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int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base);
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void clk_stm32_enable_critical_clocks(void);
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struct stm32_clk_priv *clk_stm32_get_priv(void);
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int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id);
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const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id);
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void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass);
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void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv);
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void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css);
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int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on);
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int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on);
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int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id);
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int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id);
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const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id);
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const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id);
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int clk_stm32_get_counter(unsigned long binding_id);
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void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id);
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int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id);
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int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id);
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int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel);
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int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id);
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int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx);
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int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id);
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unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id);
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unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id);
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bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag);
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int _clk_stm32_enable(struct stm32_clk_priv *priv, int id);
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void _clk_stm32_disable(struct stm32_clk_priv *priv, int id);
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int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id);
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void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id);
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bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id);
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int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id,
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unsigned long rate, unsigned long parent_rate);
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int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
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unsigned long prate);
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unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv,
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int div_id,
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unsigned long prate);
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unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx,
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unsigned long prate);
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int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx);
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void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx);
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bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id);
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bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx);
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uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id);
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int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value);
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int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel);
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int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id);
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int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb);
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#ifdef CFG_STM32_CLK_DEBUG
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void clk_stm32_display_clock_info(void);
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#endif
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struct clk_stm32_div_cfg {
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int id;
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};
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#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_binding),\
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.parent = (_parent),\
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.flags = (_flags),\
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.clock_cfg = &(struct clk_stm32_div_cfg){\
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.id = (_div_id),\
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},\
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.ops = &clk_stm32_divider_ops,\
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}
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struct clk_stm32_gate_cfg {
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int id;
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};
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#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_binding),\
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.parent = (_parent),\
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.flags = (_flags),\
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.clock_cfg = &(struct clk_stm32_gate_cfg){\
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.id = (_gate_id),\
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},\
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.ops = &clk_stm32_gate_ops,\
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}
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struct fixed_factor_cfg {
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unsigned int mult;
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unsigned int div;
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};
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unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
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int _idx, unsigned long prate);
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#define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_idx),\
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.parent = (_parent),\
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.clock_cfg = &(struct fixed_factor_cfg){\
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.mult = (_mult),\
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.div = (_div),\
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},\
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.ops = &clk_fixed_factor_ops,\
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}
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#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_binding),\
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.parent = (_parent),\
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.flags = (_flags),\
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.clock_cfg = &(struct clk_gate_cfg){\
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.offset = (_offset),\
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.bit_idx = (_bit_idx),\
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},\
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.ops = &clk_gate_ops,\
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}
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#define STM32_MUX(idx, _binding, _mux_id, _flags) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_binding),\
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.parent = (MUX(_mux_id)),\
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.flags = (_flags),\
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.clock_cfg = NULL,\
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.ops = (&clk_mux_ops),\
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}
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struct clk_timer_cfg {
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uint32_t apbdiv;
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uint32_t timpre;
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};
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#define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_idx),\
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.parent = (_parent),\
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.flags = (CLK_SET_RATE_PARENT | (_flags)),\
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.clock_cfg = &(struct clk_timer_cfg){\
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.apbdiv = (_apbdiv),\
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.timpre = (_timpre),\
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},\
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.ops = &clk_timer_ops,\
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}
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struct clk_stm32_fixed_rate_cfg {
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unsigned long rate;
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};
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#define CLK_FIXED_RATE(idx, _binding, _rate) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_binding),\
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.parent = (CLK_IS_ROOT),\
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.clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\
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.rate = (_rate),\
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},\
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.ops = &clk_stm32_fixed_rate_ops,\
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}
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#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\
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.offset = (_offset),\
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.bit_byp = (_bit_byp),\
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.bit_digbyp = (_bit_digbyp),\
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}
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#define CSS(_offset, _bit_css) &(struct stm32_clk_css){\
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.offset = (_offset),\
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.bit_css = (_bit_css),\
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}
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#define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\
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.offset = (_offset),\
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.drv_shift = (_shift),\
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.drv_width = (_width),\
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.drv_default = (_default),\
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}
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#define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \
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[(idx_osc)] = (struct clk_oscillator_data){\
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.name = (_name),\
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.id_clk = (_id),\
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.gate_id = (_gate_id),\
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.gate_rdy_id = (_gate_rdy_id),\
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.bypass = (_bypass),\
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.css = (_css),\
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.drive = (_drive),\
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}
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struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id);
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void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id);
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bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id);
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int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id);
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void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id);
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struct stm32_osc_cfg {
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int osc_id;
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};
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#define CLK_OSC(idx, _idx, _parent, _osc_id) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_idx),\
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.parent = (_parent),\
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.flags = CLK_IS_CRITICAL,\
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.clock_cfg = &(struct stm32_osc_cfg){\
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.osc_id = (_osc_id),\
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},\
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.ops = &clk_stm32_osc_ops,\
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}
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#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \
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[(idx)] = (struct clk_stm32){ \
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.name = #idx,\
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.binding = (_idx),\
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.parent = (_parent),\
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.flags = CLK_IS_CRITICAL,\
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.clock_cfg = &(struct stm32_osc_cfg){\
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.osc_id = (_osc_id),\
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},\
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.ops = &clk_stm32_osc_nogate_ops,\
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}
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extern const struct stm32_clk_ops clk_mux_ops;
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extern const struct stm32_clk_ops clk_stm32_divider_ops;
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extern const struct stm32_clk_ops clk_stm32_gate_ops;
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extern const struct stm32_clk_ops clk_fixed_factor_ops;
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extern const struct stm32_clk_ops clk_gate_ops;
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extern const struct stm32_clk_ops clk_timer_ops;
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extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops;
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extern const struct stm32_clk_ops clk_stm32_osc_ops;
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extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops;
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#endif /* CLK_STM32_CORE_H */
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