156 lines
5.2 KiB
C
156 lines
5.2 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/bl_aux_params/bl_aux_params.h>
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#include <lib/coreboot.h>
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#include <lib/spinlock.h>
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#include <platform.h>
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#include <qti_interrupt_svc.h>
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#include <qti_plat.h>
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#include <qti_uart_console.h>
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#include <qtiseclib_interface.h>
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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static entry_point_info_t bl33_image_ep_info;
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/*
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* Variable to hold counter frequency for the CPU's generic timer. In this
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* platform coreboot image configure counter frequency for boot core before
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* reaching TF-A.
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*/
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static uint64_t g_qti_cpu_cntfrq;
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/*
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* Lock variable to serialize cpuss reset execution.
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*/
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spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"),
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aligned(CACHE_WRITEBACK_GRANULE))) = {0x0};
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/*
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* Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
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* Any other value means cold booted.
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*/
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uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0;
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/*******************************************************************************
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* Perform any BL31 early platform setup common to ARM standard platforms.
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* Here is an opportunity to copy parameters passed by the calling EL (S-EL1
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* in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
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* done before the MMU is initialized so that the memory layout can be used
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* while creating page tables. BL2 has flushed this information to memory, so
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* we are guaranteed to pick up good data.
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******************************************************************************/
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void bl31_early_platform_setup(u_register_t from_bl2,
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u_register_t plat_params_from_bl2)
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{
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g_qti_cpu_cntfrq = read_cntfrq_el0();
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bl_aux_params_parse(plat_params_from_bl2, NULL);
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#if COREBOOT
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if (coreboot_serial.baseaddr != 0) {
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static console_t g_qti_console_uart;
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qti_console_uart_register(&g_qti_console_uart,
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coreboot_serial.baseaddr);
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}
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#endif
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl31_early_platform_setup(arg0, arg1);
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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qti_setup_page_tables(BL_CODE_BASE,
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BL_COHERENT_RAM_END - BL_CODE_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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enable_mmu_el3(0);
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}
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/*******************************************************************************
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* Perform any BL31 platform setup common to ARM standard platforms
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* Initialize the GIC driver, CPU and distributor interfaces */
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plat_qti_gic_driver_init();
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plat_qti_gic_init();
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qti_interrupt_svc_init();
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qtiseclib_bl31_platform_setup();
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/* set boot state to cold boot complete. */
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g_qti_bl31_cold_booted = 0x1;
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for the
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* security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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/* QTI platform don't have BL32 implementation. */
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assert(type == NON_SECURE);
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assert(bl33_image_ep_info.h.type == PARAM_EP);
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assert(bl33_image_ep_info.h.attr == NON_SECURE);
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/*
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* None of the images on the platforms can have 0x0
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* as the entrypoint.
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*/
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if (bl33_image_ep_info.pc) {
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return &bl33_image_ep_info;
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} else {
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return NULL;
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}
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}
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/*******************************************************************************
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* This function is used by the architecture setup code to retrieve the counter
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* frequency for the CPU's generic timer. This value will be programmed into the
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* CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency
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* of the system counter, which is retrieved from the first entry in the
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* frequency modes table. This will be used later in warm boot (psci_arch_setup)
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* of CPUs to set when CPU frequency.
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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{
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assert(g_qti_cpu_cntfrq != 0);
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return g_qti_cpu_cntfrq;
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}
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